On Mon, 31 Jan 2022 18:10:04 -0800 Dan Williams <dan.j.williams@xxxxxxxxx> wrote: > The core houses infrastructure for decoder resources. A CXL port's > dports are more closely related to decoder infrastructure than topology > enumeration. Implement generic PCI based dport enumeration in the core, > i.e. arrange for existing root port enumeration from cxl_acpi to share > code with switch port enumeration which just amounts to a small > difference in a pci_walk_bus() invocation once the appropriate 'struct > pci_bus' has been retrieved. > > Set the convention that decoder objects are registered after all dports > are enumerated. This enables userspace to know when the CXL core is > finished establishing 'dportX' links underneath the 'portX' object. > > Signed-off-by: Dan Williams <dan.j.williams@xxxxxxxxx> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx>
