On Sun, 23 Jan 2022 16:29:53 -0800
Dan Williams <dan.j.williams@xxxxxxxxx> wrote:
> From: Ben Widawsky <ben.widawsky@xxxxxxxxx>
>
> In preparation for proving CXL subsystem usage of the device_lock()
> order track the depth of ports with the expectation that shallower port
It's nitpick Monday: double space before shallower.
> locks can be held over deeper port locks.
>
> Signed-off-by: Ben Widawsky <ben.widawsky@xxxxxxxxx>
> Signed-off-by: Dan Williams <dan.j.williams@xxxxxxxxx>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx>
> ---
> drivers/cxl/core/port.c | 2 ++
> drivers/cxl/cxl.h | 2 ++
> 2 files changed, 4 insertions(+)
>
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index 826b300ba950..4ec5febf73fb 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -362,6 +362,8 @@ struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport,
> if (IS_ERR(port))
> return port;
>
> + if (parent_port)
> + port->depth = parent_port->depth + 1;
> dev = &port->dev;
> if (parent_port)
> rc = dev_set_name(dev, "port%d", port->id);
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index e60878ab4569..c1dc53492773 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -252,6 +252,7 @@ struct cxl_walk_context {
> * @dports: cxl_dport instances referenced by decoders
> * @decoder_ida: allocator for decoder ids
> * @component_reg_phys: component register capability base address (optional)
> + * @depth: How deep this port is relative to the root. depth 0 is the root.
> */
> struct cxl_port {
> struct device dev;
> @@ -260,6 +261,7 @@ struct cxl_port {
> struct list_head dports;
> struct ida decoder_ida;
> resource_size_t component_reg_phys;
> + unsigned int depth;
> };
>
> /**
>
