Hi, Kishon
- src_addr = dma_alloc_coherent(dev, size, &src_phys_addr, GFP_KERNEL);
- if (!src_addr) {
+ orig_src_addr = dma_alloc_coherent(dev, size + alignment,
+ &orig_src_phys_addr, GFP_KERNEL);
I noticed in the changes below from this commit[1], you allocate "size + alignment" dma buffer instead of "size" only, but IIUC, the size of dma_alloc_coherent doesn't need to add the extra "alignment".
Is the alignment here used to reserve memory?
I have no K2G EP, but when I use cadence's controller as EP, and use "size" instead of "size + alignment" for alloc size, it doesn't have any problem, and crc32 is correct when using userspace tool "pcitest"[2] to read and write 1-300 bytes.
Hi, Tom
On cadence PCIe's userdoc 4.5.6.8.4. AXI Region Base Address Registers, it says axi_addr0's [5:0] bits are used for the programmed value of size:
> The programmed value in this field + 1 gives the region size. Minimum value to be programmed into this field is 7 as the lower 8 bits of the AXI region base address are replaced by zeros by the region select logic. Minimum region size supported is 256 bytes.
Is this why cdns_pcie_epc_features's align is 256 bytes. So, should dma_alloc_coherent's size below be at least 256 bytes?
[^1]: https://patchwork.kernel.org/project/linux-omap/patch/20170818145810.17649-15-kishon@xxxxxx/
[^2]: https://www.kernel.org/doc/html/latest/PCI/endpoint/pci-test-howto.html
Regards,
Li
