On 1/23/22 16:31, Pali Rohár wrote:
On Saturday 22 January 2022 23:15:54 marek.vasut@xxxxxxxxx wrote:
From: Marek Vasut <marek.vasut+renesas@xxxxxxxxx>
In case the controller is transitioning to L1 in rcar_pcie_config_access(),
any read/write access to PCIECDR triggers asynchronous external abort. This
is because the transition to L1 link state must be manually finished by the
driver. The PCIe IP can transition back from L1 state to L0 on its own.
Hello!
I must admit that this patch from its initial version evolved into giant hack...
https://lore.kernel.org/linux-pci/20210514200549.431275-1-marek.vasut@xxxxxxxxx/
During review of the previous patch I have asked some important
questions but I have not got any answer to them. So I'm reminding it:
https://lore.kernel.org/linux-pci/20210805183024.ftdwknkttfwwogks@pali/
So could please answer what happens when PCIe controller is in some
non-L* state and either MMIO happen or config read happens or config
write happens?
What kind of non-L state ?
Do you have some specific test which fails ?
This patch addresses the case where the link transition to L1 state has
to be completed manually. If the CPU accesses the config space before
that happened, you get an imprecise data abort.
It is really important to know this fact.
I'm in impression that this patch still is not enough as similar issues
are also in other PCIe controllers which I know...
Do you have a suggestion for a patch which would be enough on this
hardware ?
