PCI Data Object Exchange [1] provides a mailbox interface used as the
transport for various protocols defined by PCI-SIG and others. Make the
limited information in config space available. Note the Read/Write
Mailbox registers themselves are not currently parsed as the usefulness
of accessing one dword of a protocol is probably limited.
In future, operating systems may provide means to safely query the
supported protocols, but those have not yet been defined.
Example output:
Capabilities: [190 v1] Data Object Exchange
DOECap: IntSup:+
Interrupt Message Number: 001
DOECtl: IntEn:-
DOESta: Busy:- IntSta:- Error:- ObjectReady:-
[1] Data Object Exchange (DOE) ECN, approved 12 March 2020
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx>
---
lib/header.h | 15 +++
ls-ecaps.c | 38 +++++++
tests/cap-doe | 302 ++++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 355 insertions(+)
diff --git a/lib/header.h b/lib/header.h
index d4b40aa..85414bc 100644
--- a/lib/header.h
+++ b/lib/header.h
@@ -252,6 +252,7 @@
#define PCI_EXT_CAP_ID_LMR 0x27 /* Lane Margining at Receiver */
#define PCI_EXT_CAP_ID_HIER_ID 0x28 /* Hierarchy ID */
#define PCI_EXT_CAP_ID_NPEM 0x29 /* Native PCIe Enclosure Management */
+#define PCI_EXT_CAP_ID_DOE 0x2e /* Data Object Exchange */
/*** Definitions of capabilities ***/
@@ -1253,6 +1254,20 @@
#define PCI_L1PM_SUBSTAT_CTL1_ASPM_L11 0x8 /* ASPM L1.1 Enable */
#define PCI_L1PM_SUBSTAT_CTL2 0xC /* L1 PM Substate Control 2 */
+/* Data Object Exchange Extended Capability */
+#define PCI_DOE_CAP 0x4 /* DOE Capabilities Register */
+#define PCI_DOE_CAP_INT_SUPP 0x1 /* Interrupt Support */
+#define PCI_DOE_CAP_INT_MSG(x) (((x) >> 1) & 0x7ff) /* DOE Interrupt Message Number */
+#define PCI_DOE_CTL 0x8 /* DOE Control Register */
+#define PCI_DOE_CTL_ABORT 0x1 /* DOE Abort */
+#define PCI_DOE_CTL_INT 0x2 /* DOE Interrupt Enable */
+#define PCI_DOE_CTL_GO 0x80000000 /* DOE Go */
+#define PCI_DOE_STS 0xC /* DOE Status Register */
+#define PCI_DOE_STS_BUSY 0x1 /* DOE Busy */
+#define PCI_DOE_STS_INT 0x2 /* DOE Interrupt Status */
+#define PCI_DOE_STS_ERROR 0x3 /* DOE Error */
+#define PCI_DOE_STS_OBJECT_READY 0x80000000 /* Data Object Ready */
+
/*
* The PCI interface treats multi-function devices as independent
* devices. The slot/function address of each device is encoded
diff --git a/ls-ecaps.c b/ls-ecaps.c
index 99c55ff..dd328c3 100644
--- a/ls-ecaps.c
+++ b/ls-ecaps.c
@@ -992,6 +992,41 @@ cap_rebar(struct device *d, int where, int virtual)
}
}
+static void
+cap_doe(struct device *d, int where)
+{
+ u32 l;
+
+ printf("Data Object Exchange\n");
+
+ if (verbose < 2)
+ return;
+
+ if (!config_fetch(d, where + PCI_DOE_CAP, 0x14))
+ {
+ printf("\t\t<unreadable>\n");
+ return;
+ }
+
+ l = get_conf_long(d, where + PCI_DOE_CAP);
+ printf("\t\tDOECap: IntSup:%c\n",
+ FLAG(l, PCI_DOE_CAP_INT_SUPP));
+ if (l & PCI_DOE_CAP_INT_SUPP)
+ printf("\t\t\tInterrupt Message Number: %03x\n",
+ PCI_DOE_CAP_INT_MSG(l));
+
+ l = get_conf_long(d, where + PCI_DOE_CTL);
+ printf("\t\tDOECtl: IntEn:%c\n",
+ FLAG(l, PCI_DOE_CTL_INT));
+
+ l = get_conf_long(d, where + PCI_DOE_STS);
+ printf("\t\tDOESta: Busy:%c IntSta:%c Error:%c ObjectReady:%c\n",
+ FLAG(l, PCI_DOE_STS_BUSY),
+ FLAG(l, PCI_DOE_STS_INT),
+ FLAG(l, PCI_DOE_STS_ERROR),
+ FLAG(l, PCI_DOE_STS_OBJECT_READY));
+}
+
void
show_ext_caps(struct device *d, int type)
{
@@ -1139,6 +1174,9 @@ show_ext_caps(struct device *d, int type)
case PCI_EXT_CAP_ID_NPEM:
printf("Native PCIe Enclosure Management <?>\n");
break;
+ case PCI_EXT_CAP_ID_DOE:
+ cap_doe(d, where);
+ break;
default:
printf("Extended Capability ID %#02x\n", id);
break;
diff --git a/tests/cap-doe b/tests/cap-doe
new file mode 100644
index 0000000..4edc3e7
--- /dev/null
+++ b/tests/cap-doe
@@ -0,0 +1,302 @@
+df:00.0 Memory controller [0502]: Intel Corporation Device 0d93 (rev 01) (prog-if 10)
+ Subsystem: Red Hat, Inc. Device 1100
+ Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Interrupt: pin ? routed to IRQ 255
+ Region 0: Memory at 10800000 (64-bit, non-prefetchable) [disabled]
+ Region 2: Memory at 10810000 (64-bit, non-prefetchable) [disabled]
+ Region 4: Memory at 10811000 (32-bit, non-prefetchable) [disabled]
+ Capabilities: [40] MSI-X: Enable- Count=2 Masked-
+ Vector table: BAR=4 offset=00000000
+ PBA: BAR=4 offset=00000800
+ Capabilities: [80] Express (v2) Endpoint, MSI 00
+ DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us
+ ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- SlotPowerLimit 0W
+ DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq-
+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
+ MaxPayload 128 bytes, MaxReadReq 128 bytes
+ DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend-
+ LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s, Exit Latency L0s <64ns
+ ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp-
+ LnkCtl: ASPM Disabled; RCB 64 bytes, Disabled- CommClk-
+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
+ LnkSta: Speed 2.5GT/s (ok), Width x1 (ok)
+ TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt-
+ DevCap2: Completion Timeout: Not Supported, TimeoutDis- NROPrPrP- LTR-
+ 10BitTagComp- 10BitTagReq- OBFF Not Supported, ExtFmt+ EETLPPrefix+, MaxEETLPPrefixes 4
+ EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
+ FRS- TPHComp- ExtTPHComp-
+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LTR- 10BitTagReq- OBFF Disabled,
+ AtomicOpsCtl: ReqEn-
+ LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-
+ Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
+ Compliance Preset/De-emphasis: -6dB de-emphasis, 0dB preshoot
+ LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete- EqualizationPhase1-
+ EqualizationPhase2- EqualizationPhase3- LinkEqualizationRequest-
+ Retimer- 2Retimers- CrosslinkRes: unsupported
+ Capabilities: [100 v1] Data Object Exchange
+ DOECap: IntSup:+
+ Interrupt Message Number: 001
+ DOECtl: IntEn:+
+ DOESta: Busy:- IntSta:- Error:- ObjectReady:+
+ Capabilities: [130 v1] Data Object Exchange
+ DOECap: IntSup:-
+ DOECtl: IntEn:-
+ DOESta: Busy:- IntSta:- Error:- ObjectReady:-
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+
--
2.19.1
