On 1/14/22 12:48, Pali Rohár wrote:
On Friday 14 January 2022 08:58:34 Stefan Roese wrote:
From: Bharat Kumar Gogada <bharat.kumar.gogada@xxxxxxxxxx>
Add nwl_init_platform_service_irqs() hook to init_platform_service_irqs
to register the platform-specific Service Errors IRQs for this PCIe
controller to fully support e.g. AER on this platform.
Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xxxxxxxxxx>
Signed-off-by: Stefan Roese <sr@xxxxxxx>
Cc: Bjorn Helgaas <helgaas@xxxxxxxxxx>
Cc: Pali Rohár <pali@xxxxxxxxxx>
Cc: Michal Simek <michal.simek@xxxxxxxxxx>
Reviewed-by: Pali Rohár <pali@xxxxxxxxxx>
---
drivers/pci/controller/pcie-xilinx-nwl.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c
index 414b679175b3..540536bbe3f8 100644
--- a/drivers/pci/controller/pcie-xilinx-nwl.c
+++ b/drivers/pci/controller/pcie-xilinx-nwl.c
@@ -24,6 +24,7 @@
#include <linux/irqchip/chained_irq.h>
#include "../pci.h"
+#include "../pcie/portdrv.h"
/* Bridge core config registers */
#define BRCFG_PCIE_RX0 0x00000000
@@ -806,6 +807,22 @@ static int nwl_pcie_parse_dt(struct nwl_pcie *pcie,
return 0;
}
+static int nwl_init_platform_service_irqs(struct pci_dev *dev, int *irqs,
+ int plat_mask)
+{
+ struct pci_host_bridge *bridge;
+ struct nwl_pcie *pcie;
+
+ bridge = pci_find_host_bridge(dev->bus);
+ pcie = pci_host_bridge_priv(bridge);
+ if (plat_mask & PCIE_PORT_SERVICE_AER) {
+ irqs[PCIE_PORT_SERVICE_AER_SHIFT] = pcie->irq_misc;
+ return 0; /* platform-specific service IRQ installed */
+ }
Just I want to be sure, with this change PME and HP interrupts are not
provided even when plat_mask argument contains them.
This function is only used for Root Ports. E.g. HP at the downstream
ports of the PCIe switch still works in our case, as here
pcie_init_service_irqs() still gets called:
# cat /proc/interrupts | grep pci
44: 0 0 0 0 GICv2 150 Level
nwl_pcie:misc, aerdrv
61: 2 0 0 0 nwl_pcie:msi 1064960
Edge pciehp
63: 0 0 0 0 nwl_pcie:msi 1081344
Edge pciehp
65: 4 0 0 0 nwl_pcie:msi 1097728
Edge pciehp
Thanks,
Stefan
+
+ return -ENODEV; /* platform-specific service IRQ not installed */
+}
+
static const struct of_device_id nwl_pcie_of_match[] = {
{ .compatible = "xlnx,nwl-pcie-2.11", },
{}
@@ -857,6 +874,7 @@ static int nwl_pcie_probe(struct platform_device *pdev)
bridge->sysdata = pcie;
bridge->ops = &nwl_pcie_ops;
+ bridge->init_platform_service_irqs = nwl_init_platform_service_irqs;
if (IS_ENABLED(CONFIG_PCI_MSI)) {
err = nwl_pcie_enable_msi(pcie);
--
2.34.1
Viele Grüße,
Stefan Roese
--
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