On Thu, Nov 25, 2021 at 01:45:58PM +0100, Pali Rohár wrote: > Properly propagate failure from mvebu_pcie_add_windows() function back to > the caller mvebu_pci_bridge_emul_base_conf_write() and correctly updates > PCI_IO_BASE, PCI_MEM_BASE and PCI_IO_BASE_UPPER16 registers on error. > On error set base value higher than limit value which indicates that > address range is disabled. Does the spec say that if software programs something invalid, hardware should proactively set the base and limit registers to disable the window? I'm not sure I've seen hardware that does this, and it seems ... maybe a little aggressive. What happens if software writes the base and limit in the wrong order, so the window is invalid after the first write but valid after the second? That actually sounds like it could be a sensible strategy to prevent a partially-configured window from being active. Bjorn
