On Mon, 27 Dec 2021 21:31:10 +0800, qizhong cheng wrote: > Described in PCIe CEM specification sections 2.2 (PERST# Signal) and > 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should > be delayed 100ms (TPVPERL) for the power and clock to become stable. > > Applied to pci/mediatek, thanks! [1/1] PCI: mediatek: Assert PERST# for 100ms for power and clock to stabilize https://git.kernel.org/lpieralisi/pci/c/65ace9a85f Thanks, Lorenzo