Hi Pali, On 1/5/2022 1:35 AM, Pali Rohár wrote: > Register 0x43c in its low 24 bits contains PCI class code. > > Update code to set all 24 bits of PCI class code and not only upper 16 bits > of PCI class code. > > Use a new macro PCI_CLASS_BRIDGE_PCI_NORMAL which represents whole 24 bits > of normal PCI bridge class. > > Signed-off-by: Pali Rohár <pali@xxxxxxxxxx> > > --- > Roman helped me with this change and confirmed that class code is stored > really in bits [23:0] of custom register 0x43c (normally class code is > stored in bits [31:8] of pci register 0x08). > > This patch depends on patch which adds PCI_CLASS_BRIDGE_PCI_NORMAL macro: > https://lore.kernel.org/linux-pci/20211220145140.31898-1-pali@xxxxxxxxxx/ > --- > drivers/pci/controller/pcie-iproc.c | 9 ++++----- > 1 file changed, 4 insertions(+), 5 deletions(-) > > diff --git a/drivers/pci/controller/pcie-iproc.c b/drivers/pci/controller/pcie-iproc.c > index 3df4ab209253..2519201b0e51 100644 > --- a/drivers/pci/controller/pcie-iproc.c > +++ b/drivers/pci/controller/pcie-iproc.c > @@ -789,14 +789,13 @@ static int iproc_pcie_check_link(struct iproc_pcie *pcie) > return -EFAULT; > } > > - /* force class to PCI_CLASS_BRIDGE_PCI (0x0604) */ > + /* force class to PCI_CLASS_BRIDGE_PCI_NORMAL (0x060400) */ > #define PCI_BRIDGE_CTRL_REG_OFFSET 0x43c > -#define PCI_CLASS_BRIDGE_MASK 0xffff00 > -#define PCI_CLASS_BRIDGE_SHIFT 8 > +#define PCI_BRIDGE_CTRL_REG_CLASS_MASK 0xffffff > iproc_pci_raw_config_read32(pcie, 0, PCI_BRIDGE_CTRL_REG_OFFSET, > 4, &class); > - class &= ~PCI_CLASS_BRIDGE_MASK; > - class |= (PCI_CLASS_BRIDGE_PCI << PCI_CLASS_BRIDGE_SHIFT); > + class &= ~PCI_BRIDGE_CTRL_REG_CLASS_MASK; > + class |= PCI_CLASS_BRIDGE_PCI_NORMAL; > iproc_pci_raw_config_write32(pcie, 0, PCI_BRIDGE_CTRL_REG_OFFSET, > 4, class); > I have two comments: 1. You do not seem to generate the email list using the get_maintainer.pl script, so the two maintainers for Broadcom ARM architecture (Ray Jui and Scott Branden) are left out. 2. I suppose 'PCI_CLASS_BRIDGE_PCI_NORMAL' is defined in some common PCI header in a separate patch as described in the commit message. Then how come these patches are not constructed with a patch series? Other than, the change itself is exactly what I sent to Roman and looks good to me. Thanks. Acked-by: Ray Jui <ray.jui@xxxxxxxxxxxx>
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