On Wednesday 05 January 2022 09:41:51 Rob Herring wrote:
> > @@ -347,6 +375,11 @@ static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port,
> > return PCIBIOS_SUCCESSFUL;
> > }
> >
> > +static struct pci_ops mvebu_pcie_child_ops = {
> > + .read = mvebu_pcie_child_rd_conf,
> > + .write = mvebu_pcie_child_wr_conf,
> > +};
> > +
> > /*
> > * Remove windows, starting from the largest ones to the smallest
> > * ones.
> > @@ -862,25 +895,12 @@ static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
> > {
> > struct mvebu_pcie *pcie = bus->sysdata;
> > struct mvebu_pcie_port *port;
> > - int ret;
> >
> > port = mvebu_pcie_find_port(pcie, bus, devfn);
> > if (!port)
> > return PCIBIOS_DEVICE_NOT_FOUND;
>
> It would be nice to go from 'bus' to 'bridge' ptr directly, but I
> still had this in my version. I guess a standard RP struct as part of
> decoupling host bridges from RPs would solve this issue.
Hello!
The problem is somewhere else. This driver is misusing bus 0 for doing
non-transparent bus-bridging between multiple PCI domains by registering
roots ports across all domains into domain 0, bus 0. All details are
in this my patch which documents this strange driver behavior:
https://lore.kernel.org/linux-pci/20211125124605.25915-12-pali@xxxxxxxxxx/
So the correct solution is is split these multidomain mixing and then
every domain would have exactly one root port (as it is designed in HW).
