在 2021/12/16 13:50, Arnd Bergmann 写道:
On Thu, Dec 16, 2021 at 2:07 PM Jiaxun Yang <jiaxun.yang@xxxxxxxxxxx> wrote:
在2021年12月16日十二月 上午11:44，Xi Ruoyao写道：
Another way could be keeping a linked list about PIO->PHYS mapping instead of using the single io_port_base variable.
I think that would add a lot of complexity that isn't needed here. Not
sure if all MIPS CPUs
can do it, but the approach used on Arm is what fits in best with the
PCI drivers, these
reserve a virtual address range for the ports, and ioremap the
physical addresses into
the PIO range according to the mapping.
Yes, the Arm way was my previous approach when introducing PCI IO map
for Loongson.
It got refactored by this patch as TLB entries are expensive on MIPS,
also the size of IO range doesn't always fits a page.
For the loongson case specifically, that's not even needed though, as
the two buses
have physically contiguous I/O port ranges, the code just needs to
detect this special
case.
We have MIPS Boston board (from imgtec) which has discontinuous IO
range.
Thanks.
Arnd
- Jiaxun
