There are two different PCIe controllers and PHYs on SM8450, one having
one lane and another with two lanes. This set of patches adds support
for the first PCIe phy and controller only, support for the second PCIe
part will come later.
Changes since v1:
- Fix capitalization/wording of PCI patch subjects
- Add missing gen3x1 specification to PHY table names
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Dmitry Baryshkov (10):
dt-bindings: pci: qcom: Document PCIe bindings for SM8450
dt-bindings: phy: qcom,qmp: Add SM8450 PCIe PHY bindings
phy: qcom-qmp: Add SM8450 PCIe0 PHY support
PCI: qcom: Remove redundancy between qcom_pcie and qcom_pcie_cfg
PCI: qcom: Add ddrss_sf_tbu flag
PCI: qcom: Add SM8450 PCIe support
arm64: dts: qcom: sm8450: add PCIe0 PHY node
arm64: dts: qcom: sm8450: add PCIe0 RC device
arm64: dts: qcom: sm8450-qrd: enable PCIe0 PHY device
arm64: dts: qcom: sm8450-qrd: enable PCIe0 host
.../devicetree/bindings/pci/qcom,pcie.txt | 21 ++-
.../devicetree/bindings/phy/qcom,qmp-phy.yaml | 2 +
arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 14 ++
arch/arm64/boot/dts/qcom/sm8450.dtsi | 143 ++++++++++++++++++++-
drivers/pci/controller/dwc/pcie-qcom.c | 89 ++++++++-----
drivers/phy/qualcomm/phy-qcom-qmp.c | 125 ++++++++++++++++++
drivers/phy/qualcomm/phy-qcom-qmp.h | 33 +++++
7 files changed, 389 insertions(+), 38 deletions(-)
