On Thu, Nov 04, 2021 at 02:21:44PM +0800, qizhong cheng wrote: > Described in PCIe CEM specification setctions 2.2 (PERST# Signal) and > 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should > be delayed 100ms (TPVPERL) for the power and clock to become stable. Thanks for the spec references. s/setctions/sections/ > Signed-off-by: qizhong cheng <qizhong.cheng@xxxxxxxxxxxx> > --- > drivers/pci/controller/pcie-mediatek.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c > index 2f3f974977a3..b32acbac8084 100644 > --- a/drivers/pci/controller/pcie-mediatek.c > +++ b/drivers/pci/controller/pcie-mediatek.c > @@ -702,6 +702,14 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) > */ > writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); > > + /* > + * Described in PCIe CEM specification setctions 2.2 (PERST# Signal) > + * and 2.2.1 (Initial Power-Up (G3 to S0)). > + * The deassertion of PERST# should be delayed 100ms (TPVPERL) > + * for the power and clock to become stable. s/setctions/sections/ again. Otherwise we'll have a typo-fixing patch eventually. Please also rewrap into one paragraph. > + */ > + msleep(100); > + > /* De-assert PHY, PE, PIPE, MAC and configuration reset */ > val = readl(port->base + PCIE_RST_CTRL); > val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB | > -- > 2.25.1 >
