On Thu, Nov 18, 2021 at 10:48 PM Christoph Hellwig <hch@xxxxxx> wrote: > > On Wed, Nov 17, 2021 at 04:15:36PM -0600, Bjorn Helgaas wrote: > > > Agreed though how it all gets tied together isn't totally clear > > > to me yet. The messy bit is interrupts given I don't think we have > > > a model for enabling those anywhere other than in individual PCI drivers. > > > > Ah. Yeah, that is a little messy. The only real precedent where the > > PCI core and a driver might need to coordinate on interrupts is the > > portdrv. So far we've pretended that bridges do not have > > device-specific functionality that might require interrupts. I don't > > think that's actually true, but we haven't integrated drivers for the > > tuning, performance monitoring, and similar features that bridges may > > have. Yet. > > And portdrv really is conceptually part of the core PCI core, and > should eventually be fully integrated.. What does a fully integrated portdrv look like? DOE enabling could follow a similar model. > > > In any case, I think the argument that DOE capabilities are not > > CXL-specific still holds. > > Agreed. I don't think anyone is arguing that DOE is something CXL specific. The enabling belongs only in drivers/pci/ as a DOE core, and then that core is referenced by any other random PCI driver that needs to interact with a DOE. The question is what does that DOE core look like? A Linux device representing the DOE capability and a common driver for the data-transfer seems a reasonable abstraction to me and that's what Auxiliary Bus offers.
