On Sun, Oct 31, 2021 at 07:12:28PM +0100, Marek Behún wrote:
> From: Pali Rohár <pali@xxxxxxxxxx>
>
> pci-bridge-emul driver already allocates buffer for capabilities up to the
> PCI_EXP_SLTSTA2 register, but does not define bit access behavior for these
> registers. Add these missing definitions.
>
> Signed-off-by: Pali Rohár <pali@xxxxxxxxxx>
> Signed-off-by: Marek Behún <kabel@xxxxxxxxxx>
> Cc: stable@xxxxxxxxxxxxxxx
Is this tag in preparation for something else ? I don't even think this
is a fix per-se.
Lorenzo
> ---
> drivers/pci/pci-bridge-emul.c | 39 +++++++++++++++++++++++++++++++++++
> 1 file changed, 39 insertions(+)
>
> diff --git a/drivers/pci/pci-bridge-emul.c b/drivers/pci/pci-bridge-emul.c
> index a4af1a533d71..aa3320e3c469 100644
> --- a/drivers/pci/pci-bridge-emul.c
> +++ b/drivers/pci/pci-bridge-emul.c
> @@ -251,6 +251,45 @@ struct pci_bridge_reg_behavior pcie_cap_regs_behavior[PCI_CAP_PCIE_SIZEOF / 4] =
> .ro = GENMASK(15, 0) | PCI_EXP_RTSTA_PENDING,
> .w1c = PCI_EXP_RTSTA_PME,
> },
> +
> + [PCI_EXP_DEVCAP2 / 4] = {
> + /* Device capabilities 2 register has reserved bits [30:27]. */
> + .ro = BIT(31) | GENMASK(26, 0),
> + },
> +
> + [PCI_EXP_DEVCTL2 / 4] = {
> + /*
> + * Device control 2 register is RW.
> + *
> + * Device status 2 register is reserved.
> + */
> + .rw = GENMASK(15, 0),
> + },
> +
> + [PCI_EXP_LNKCAP2 / 4] = {
> + /* Link capabilities 2 register has reserved bits [30:25] and 0. */
> + .ro = BIT(31) | GENMASK(24, 1),
> + },
> +
> + [PCI_EXP_LNKCTL2 / 4] = {
> + /*
> + * Link control 2 register is RW.
> + *
> + * Link status 2 register has bits 5, 15 W1C;
> + * bits 10, 11 reserved and others are RO.
> + */
> + .rw = GENMASK(15, 0),
> + .w1c = (BIT(15) | BIT(5)) << 16,
> + .ro = (GENMASK(14, 12) | GENMASK(9, 6) | GENMASK(4, 0)) << 16,
> + },
> +
> + [PCI_EXP_SLTCAP2 / 4] = {
> + /* Slot capabilities 2 register is reserved. */
> + },
> +
> + [PCI_EXP_SLTCTL2 / 4] = {
> + /* Both Slot control 2 and Slot status 2 registers are reserved. */
> + },
> };
>
> /*
> --
> 2.32.0
>
