On Fri, 19 Nov 2021 16:02:44 -0800
Ben Widawsky <ben.widawsky@xxxxxxxxx> wrote:
> CXL 1.1 specification provided a mechanism for mapping an address space
> of a CXL device. That functionality is known as a "range" and can be
> programmed through PCIe DVSEC. In addition to this, the specification
> defines an active bit which a device will expose through the same DVSEC
> to notify system software that memory is initialized and ready.
>
> While CXL 2.0 introduces a more powerful mechanism called HDM decoders
> that are controlled by MMIO behind a PCIe BAR, the spec does allow the
> 1.1 style mapping to still be present. In such a case, when the CXL
> driver takes over, if it were to enable HDM decoding and there was an
> actively used range, things would likely blow up, in particular if it
> wasn't an identical mapping.
>
> This patch caches the relevant information which the cxl_mem driver will
> need to make the proper decision and passes it along.
>
> Signed-off-by: Ben Widawsky <ben.widawsky@xxxxxxxxx>
> ---
> drivers/cxl/cxlmem.h | 19 +++++++
> drivers/cxl/pci.c | 126 +++++++++++++++++++++++++++++++++++++++++++
> drivers/cxl/pci.h | 13 +++++
> 3 files changed, 158 insertions(+)
>
> diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
> index 3ef3c652599e..eac5528ccaae 100644
> --- a/drivers/cxl/cxlmem.h
> +++ b/drivers/cxl/cxlmem.h
> @@ -89,6 +89,22 @@ struct cxl_mbox_cmd {
> */
> #define CXL_CAPACITY_MULTIPLIER SZ_256M
>
> +/**
> + * struct cxl_endpoint_dvsec_info - Cached DVSEC info
> + * @mem_enabled: cached value of mem_enabled in the DVSEC, PCIE_DEVICE
> + * @ranges: Number of HDM ranges this device contains.
> + * @range.base: cached value of the range base in the DVSEC, PCIE_DEVICE
> + * @range.size: cached value of the range size in the DVSEC, PCIE_DEVICE
> + */
> +struct cxl_endpoint_dvsec_info {
> + bool mem_enabled;
> + int ranges;
> + struct {
> + u64 base;
> + u64 size;
> + } range[2];
kernel-doc wants documentation for range as well.
> +};
