On Fri, Nov 19, 2021 at 4:03 PM Ben Widawsky <ben.widawsky@xxxxxxxxx> wrote: > > Since the code to add decoders for switches and endpoints is on the > horizon it helps to have properly documented APIs. In addition, the > decoder APIs will never need to support a negative count for downstream > targets as the spec explicitly starts numbering them at 1, ie. even 0 is > an "invalid" value which can be used as a sentinel. Looks good to me: Reviewed-by: Dan Williams <dan.j.williams@xxxxxxxxx> > > Signed-off-by: Ben Widawsky <ben.widawsky@xxxxxxxxx> > > --- > > This is respun from a previous incantation here: > https://lore.kernel.org/linux-cxl/20210915155946.308339-1-ben.widawsky@xxxxxxxxx/ > --- > drivers/cxl/core/bus.c | 33 +++++++++++++++++++++++++++++++-- > drivers/cxl/cxl.h | 3 ++- > 2 files changed, 33 insertions(+), 3 deletions(-) > > diff --git a/drivers/cxl/core/bus.c b/drivers/cxl/core/bus.c > index 8e80e85350b1..1ee12a60f3f4 100644 > --- a/drivers/cxl/core/bus.c > +++ b/drivers/cxl/core/bus.c > @@ -495,7 +495,20 @@ static int decoder_populate_targets(struct cxl_decoder *cxld, > return rc; > } > > -struct cxl_decoder *cxl_decoder_alloc(struct cxl_port *port, int nr_targets) > +/** > + * cxl_decoder_alloc - Allocate a new CXL decoder > + * @port: owning port of this decoder > + * @nr_targets: downstream targets accessible by this decoder. All upstream > + * ports and root ports must have at least 1 target. > + * > + * A port should contain one or more decoders. Each of those decoders enable > + * some address space for CXL.mem utilization. A decoder is expected to be > + * configured by the caller before registering. > + * > + * Return: A new cxl decoder to be registered by cxl_decoder_add() > + */ > +struct cxl_decoder *cxl_decoder_alloc(struct cxl_port *port, > + unsigned int nr_targets) > { > struct cxl_decoder *cxld, cxld_const_init = { > .nr_targets = nr_targets, > @@ -503,7 +516,7 @@ struct cxl_decoder *cxl_decoder_alloc(struct cxl_port *port, int nr_targets) > struct device *dev; > int rc = 0; > > - if (nr_targets > CXL_DECODER_MAX_INTERLEAVE || nr_targets < 1) > + if (nr_targets > CXL_DECODER_MAX_INTERLEAVE || nr_targets == 0) > return ERR_PTR(-EINVAL); > > cxld = kzalloc(struct_size(cxld, target, nr_targets), GFP_KERNEL); > @@ -535,6 +548,22 @@ struct cxl_decoder *cxl_decoder_alloc(struct cxl_port *port, int nr_targets) > } > EXPORT_SYMBOL_NS_GPL(cxl_decoder_alloc, CXL); > > +/** > + * cxl_decoder_add - Add a decoder with targets > + * @cxld: The cxl decoder allocated by cxl_decoder_alloc() > + * @target_map: A list of downstream ports that this decoder can direct memory > + * traffic to. These numbers should correspond with the port number > + * in the PCIe Link Capabilities structure. > + * > + * Certain types of decoders may not have any targets. The main example of this > + * is an endpoint device. A more awkward example is a hostbridge whose root > + * ports get hot added (technically possible, though unlikely). > + * > + * Context: Process context. Takes and releases the cxld's device lock. > + * > + * Return: Negative error code if the decoder wasn't properly configured; else > + * returns 0. > + */ > int cxl_decoder_add(struct cxl_decoder *cxld, int *target_map) > { > struct cxl_port *port; > diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h > index ad816fb5bdcc..b66ed8f241c6 100644 > --- a/drivers/cxl/cxl.h > +++ b/drivers/cxl/cxl.h > @@ -288,7 +288,8 @@ int cxl_add_dport(struct cxl_port *port, struct device *dport, int port_id, > > struct cxl_decoder *to_cxl_decoder(struct device *dev); > bool is_root_decoder(struct device *dev); > -struct cxl_decoder *cxl_decoder_alloc(struct cxl_port *port, int nr_targets); > +struct cxl_decoder *cxl_decoder_alloc(struct cxl_port *port, > + unsigned int nr_targets); > int cxl_decoder_add(struct cxl_decoder *cxld, int *target_map); > int cxl_decoder_autoremove(struct device *host, struct cxl_decoder *cxld); > > -- > 2.34.0 >
