Re: [PATCH 18/23] cxl/pci: Implement wait for media active

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On 21-11-23 11:48:53, Bjorn Helgaas wrote:
> On Tue, Nov 23, 2021 at 08:04:13AM -0800, Ben Widawsky wrote:
> > On 21-11-23 11:09:34, Jonathan Cameron wrote:
> > > On Mon, 22 Nov 2021 14:57:51 -0800
> > > Ben Widawsky <ben.widawsky@xxxxxxxxx> wrote:
> > > 
> > > > On 21-11-22 17:03:35, Jonathan Cameron wrote:
> > > > > On Fri, 19 Nov 2021 16:02:45 -0800
> > > > > Ben Widawsky <ben.widawsky@xxxxxxxxx> wrote:
> > > > >   
> > > > > > CXL 2.0 8.1.3.8.2 defines "Memory_Active: When set,
> > > > > > indicates that the CXL Range 1 memory is fully initialized
> > > > > > and available for software use.  Must be set within Range 1.
> > > > > > Memory_Active_Timeout of deassertion of  
> > > ...
> > > Ah, got it. Maybe Range 1: Memory Active timeout ?
> > 
> > I can, but this is just quoted from the spec. Would this be better:
> > 
> > The CXL Type 3 Memory Device Software Guide (Revision 1.0) describes the
> > need to check media active before using HDM. CXL 2.0 8.1.3.8.2 states:
> > 
> >   Memory_Active: When set, indicates that the CXL Range 1 memory is
> >   fully initialized and available for software use. Must be set within
> >   Range 1. Memory_Active_Timeout of deassertion of reset to CXL device
> >   if CXL.mem HwInit Mode=1
> 
> That is some weird wording.  I stumbled over that, too.  I like the
> quote format better, but I still don't know what it means.
> 
> That last piece ("Memory_Active_Timeout of deassertion ...") purports
> to be a sentence, but is not.

I've reported this to the person locally who drives spec changes. Since it's now
confused multiple people, I will rewrite it with my interpretation if people
think that is more optimal.

"Memory Active bit must be set within Memory_Active_Timeout amount of time
after reset."



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