On Fri, 19 Nov 2021 16:02:34 -0800 Ben Widawsky <ben.widawsky@xxxxxxxxx> wrote: > While the new definitions are yet necessary at this point, they are > introduced at this point to help solidify the newly minted schema for > naming registers. > > Signed-off-by: Ben Widawsky <ben.widawsky@xxxxxxxxx> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxx> > > --- > This was split from > https://lore.kernel.org/linux-cxl/20211103170552.55ae5u7uvurkync6@xxxxxxxxx/T/#u > per Dan's request. > --- > drivers/cxl/pci.h | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/drivers/cxl/pci.h b/drivers/cxl/pci.h > index 29b8eaef3a0a..8ae2b4adc59d 100644 > --- a/drivers/cxl/pci.h > +++ b/drivers/cxl/pci.h > @@ -16,6 +16,21 @@ > /* CXL 2.0 8.1.3: PCIe DVSEC for CXL Device */ > #define CXL_DVSEC_PCIE_DEVICE 0 > > +/* CXL 2.0 8.1.4: Non-CXL Function Map DVSEC */ > +#define CXL_DVSEC_FUNCTION_MAP 2 > + > +/* CXL 2.0 8.1.5: CXL 2.0 Extensions DVSEC for Ports */ > +#define CXL_DVSEC_PORT_EXTENSIONS 3 > + > +/* CXL 2.0 8.1.6: GPF DVSEC for CXL Port */ > +#define CXL_DVSEC_PORT_GPF 4 > + > +/* CXL 2.0 8.1.7: GPF DVSEC for CXL Device */ > +#define CXL_DVSEC_DEVICE_GPF 5 > + > +/* CXL 2.0 8.1.8: PCIe DVSEC for Flex Bus Port */ > +#define CXL_DVSEC_PCIE_FLEXBUS_PORT 7 > + > /* CXL 2.0 8.1.9: Register Locator DVSEC */ > #define CXL_DVSEC_REG_LOCATOR 8 > #define CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET 0xC
