On Thu, Nov 11, 2021 at 03:21:37PM -0600, Li Yang wrote: > On Wed, Apr 7, 2021 at 9:13 AM Zhiqiang Hou <Zhiqiang.Hou@xxxxxxx> wrote: > > > > From: Hou Zhiqiang <Zhiqiang.Hou@xxxxxxx> > > > > This patch series is to add PCIe power management support for NXP > > Layerscape platforms. > > > > Hou Zhiqiang (6): > > PCI: layerscape: Change to use the DWC common link-up check function > > dt-bindings: pci: layerscape-pci: Add a optional property big-endian > > arm64: dts: layerscape: Add big-endian property for PCIe nodes > > dt-bindings: pci: layerscape-pci: Update the description of SCFG > > property > > arm64: dts: ls1043a: Add SCFG phandle for PCIe nodes > > PCI: layerscape: Add power management support > > > > .../bindings/pci/layerscape-pci.txt | 6 +- > > .../arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 1 + > > .../arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 6 + > > .../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 3 + > > drivers/pci/controller/dwc/pci-layerscape.c | 450 ++++++++++++++---- > > drivers/pci/controller/dwc/pcie-designware.h | 1 + > > 6 files changed, 370 insertions(+), 97 deletions(-) > > Hi Bjorn, > > I don't see any feedback on this version. Is there any chance that > the binding/driver changes can be picked up? Probably slipped through the cracks. We're in the middle of the v5.16 merge window right now. After v5.16-rc1 is tagged (probably Nov 14), rebase your series on top of that, incorporate Rob's reviewed-by, and repost it. Then Lorenzo will see it and take a look. Bjorn
