On Mon, Oct 25, 2021 at 6:24 PM Rob Herring <robh@xxxxxxxxxx> wrote: > > On Fri, Oct 22, 2021 at 10:06:54AM -0400, Jim Quinlan wrote: > > Similar to the regulator bindings found in "rockchip-pcie-host.txt", this > > allows optional regulators to be attached and controlled by the PCIe RC > > driver. That being said, this driver searches in the DT subnode (the EP > > node, eg pci@0,0) for the regulator property. > > > > The use of a regulator property in the pcie EP subnode such as > > "vpcie12v-supply" depends on a pending pullreq to the pci-bus.yaml > > file at > > > > https://github.com/devicetree-org/dt-schema/pull/54 > > > > Signed-off-by: Jim Quinlan <jim2101024@xxxxxxxxx> > > --- > > .../bindings/pci/brcm,stb-pcie.yaml | 23 +++++++++++++++++++ > > 1 file changed, 23 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml > > index b9589a0daa5c..fec13e4f6eda 100644 > > --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml > > +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml > > @@ -154,5 +154,28 @@ examples: > > <0x42000000 0x1 0x80000000 0x3 0x00000000 0x0 0x80000000>; > > brcm,enable-ssc; > > brcm,scb-sizes = <0x0000000080000000 0x0000000080000000>; > > + > > + /* PCIe bridge */ > > More specifically, the root port. > > > + pci@0,0 { > > + #address-cells = <3>; > > + #size-cells = <2>; > > + reg = <0x0 0x0 0x0 0x0 0x0>; > > + device_type = "pci"; > > + ranges; > > + > > + /* PCIe endpoint */ > > + pci@0,0 { > > + device_type = "pci"; > > This means this device is a PCI bridge which wouldn't typically be the > endpoint. Is that intended? Hi Rob, I'm not sure I understand what you are saying -- do you want the innermost node to be named something like ep-pci@0,0, and its containing node pci-bridge@0,0? Or, more likely, I'm missing the point. If my DT subtree is this pcie@8b10000 { compatible = "brcm,bcm7278-pcie"; .... pci-bridge@0,0 { reg = <0x0 0x0 0x0 0x0 0x0>; /* bus 0 */ ..... pci-ep@0,0,0 { reg = <0x10000 0x0 0x0 0x0 0x0>; /* bus 1 */ vpcie3v3-supply = <&vreg8>; ... } } } then the of_nodes appear to align correctly with the devices: $ cd /sys/devices/platform/ $ cat 8b10000.pcie/of_node/name pcie $ cat 8b10000.pcie/pci0000:00/0000:00:00.0/of_node pci-bridge $ cat 8b10000.pcie/pci0000:00/0000:00:00.0/0000:01:00.0/of_node/name pci-ep and the EP device works of course. I've even printed out the device_node structure in the EP driver's probe and it is as expected. I've noticed that examples such as "arch/arm64/boot/dts/nvidia/tegra186.dtsi" have the EP node (eg pci@1,0) directly under the host bridge DT node (pcie@10003000). I did try doing that, but the EP device's probe is given a NUL device_node pointer. I don't think it matters but our PCIe controllers only have a single root port. Please advise, Jim > > > + assigned-addresses = <0x82010000 0x0 0xf8000000 0x6 0x00000000 0x0 0x2000>; > > + reg = <0x0 0x0 0x0 0x0 0x0>; > > + compatible = "pci14e4,1688"; > > + vpcie3v3-supply = <&vreg7>; > > + > > + #address-cells = <3>; > > + #size-cells = <2>; > > + > > + ranges; > > + }; > > + }; > > }; > > }; > > -- > > 2.17.1 > > > >
