On 11/10, Pali Rohár wrote:
> On Monday 11 October 2021 23:26:33 Naveen Naidu wrote:
> > An MMIO read from a PCI device that doesn't exist or doesn't respond
> > causes a PCI error. There's no real data to return to satisfy the
> > CPU read, so most hardware fabricates ~0 data.
> >
> > Use SET_PCI_ERROR_RESPONSE() to set the error response, when a faulty
> > read occurs.
> >
> > This helps unify PCI error response checking and make error check
> > consistent and easier to find.
> >
> > Compile tested only.
> >
> > Signed-off-by: Naveen Naidu <naveennaidu479@xxxxxxxxx>
> > ---
> > drivers/pci/controller/pci-aardvark.c | 8 ++++----
> > 1 file changed, 4 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
> > index 596ebcfcc82d..dc2f820ef55f 100644
> > --- a/drivers/pci/controller/pci-aardvark.c
> > +++ b/drivers/pci/controller/pci-aardvark.c
> > @@ -894,7 +894,7 @@ static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn,
> > int ret;
> >
> > if (!advk_pcie_valid_device(pcie, bus, devfn)) {
> > - *val = 0xffffffff;
> > + SET_PCI_ERROR_RESPONSE(val);
>
> Hello! Now I'm looking at this macro, and should not it depends on
> "size" argument? If doing 8-bit or 16-bit read operation then should not
> it rather sets only low 8 bits or low 16 bits to ones?
>
Hello o/, Thank you for the review.
Yes! you are right that it should indeed depend on the "size" argument.
And that is what the SET_PCI_ERROR_RESPONSE macro does. The macro is
defined as:
#define PCI_ERROR_RESPONSE (~0ULL)
#define SET_PCI_ERROR_RESPONSE(val) (*val = ((typeof(*val))PCI_ERROR_RESPONSE))
The macro was part of "Patch 1/22" and is present here [1]. Apologies if
I added the receipient incorrectly.
[1]:
https://lore.kernel.org/linux-pci/d8e423386aad3d78bca575a7521b138508638e3b.1633972263.git.naveennaidu479@xxxxxxxxx/T/#m37295a0dcfe0d7e0f67efce3633efd7b891949c4
IIUC, the typeof(*val) helps in setting the value according to the size
of the argument.
Please let me know if my understanding is wrong.
> > return PCIBIOS_DEVICE_NOT_FOUND;
> > }
> >
> > @@ -920,7 +920,7 @@ static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn,
> > *val = CFG_RD_CRS_VAL;
> > return PCIBIOS_SUCCESSFUL;
> > }
> > - *val = 0xffffffff;
> > + SET_PCI_ERROR_RESPONSE(val);
> > return PCIBIOS_SET_FAILED;
> > }
> >
> > @@ -955,14 +955,14 @@ static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn,
> > *val = CFG_RD_CRS_VAL;
> > return PCIBIOS_SUCCESSFUL;
> > }
> > - *val = 0xffffffff;
> > + SET_PCI_ERROR_RESPONSE(val);
> > return PCIBIOS_SET_FAILED;
> > }
> >
> > /* Check PIO status and get the read result */
> > ret = advk_pcie_check_pio_status(pcie, allow_crs, val);
> > if (ret < 0) {
> > - *val = 0xffffffff;
> > + SET_PCI_ERROR_RESPONSE(val);
> > return PCIBIOS_SET_FAILED;
> > }
> >
> > --
> > 2.25.1
> >
