e8635b484f64 ("MIPS: Add Cavium OCTEON PCI support.") added MIPS
specific code to enable PCIe and AER error reporting (*irrespective
of CONFIG_PCIEAER value*) because PCI core didn't do that at the time.
Currently when CONFIG_PCIEAER=y, root port's error reporting is
enabled by aer_enable_rootport() in the aer_probe() path.
It is now no longer necessary for Octeon code to enable RP's error
reporting since it's done when PCIe bus loads the AER service driver.
Signed-off-by: Naveen Naidu <naveennaidu479@xxxxxxxxx>
---
arch/mips/pci/pci-octeon.c | 18 ------------------
1 file changed, 18 deletions(-)
diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c
index b973fc464c21..239eec8ac942 100644
--- a/arch/mips/pci/pci-octeon.c
+++ b/arch/mips/pci/pci-octeon.c
@@ -114,24 +114,6 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config);
}
- /* Find the Advanced Error Reporting capability */
- pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
- if (pos) {
- /*
- * Leave severity at HW default. This only controls if
- * errors are reported as uncorrectable or
- * correctable, not if the error is reported.
- */
- /* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */
-
- /* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */
- /* Report all errors to the root complex */
- pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND,
- PCI_ERR_ROOT_CMD_COR_EN |
- PCI_ERR_ROOT_CMD_NONFATAL_EN |
- PCI_ERR_ROOT_CMD_FATAL_EN);
- }
-
return 0;
}
--
2.25.1
