e8635b484f64 ("MIPS: Add Cavium OCTEON PCI support.") added MIPS
specific code to enable PCIe and AER error reporting (*irrespective
of CONFIG_PCIEAER value*) because PCI core didn't do that at the time.
Currently when CONFIG_PCIEAER=y, correctable/uncorrectable errors
are enabled by set_device_error_reporting() in the aer_probe()
path.
It is now no longer necessary for Octeon code to enable PCIe COR/UNCOR
errors since it's done when PCIe bus loads the AER service driver.
Signed-off-by: Naveen Naidu <naveennaidu479@xxxxxxxxx>
---
arch/mips/pci/pci-octeon.c | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c
index 2c251018075c..a82cf48f00ab 100644
--- a/arch/mips/pci/pci-octeon.c
+++ b/arch/mips/pci/pci-octeon.c
@@ -117,18 +117,13 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
/* Find the Advanced Error Reporting capability */
pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
if (pos) {
- /* Enable reporting of all uncorrectable errors */
- /* Uncorrectable Error Mask - turned on bits disable errors */
- pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0);
/*
* Leave severity at HW default. This only controls if
* errors are reported as uncorrectable or
* correctable, not if the error is reported.
*/
/* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */
- /* Enable reporting of all correctable errors */
- /* Correctable Error Mask - turned on bits disable errors */
- pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0);
+
/* Advanced Error Capabilities */
pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig);
/* ECRC Generation Enable */
--
2.25.1
