On Thu, Sep 23, 2021 at 10:27 AM Ben Widawsky <ben.widawsky@xxxxxxxxx> wrote: > > In preparation for moving parts of register mapping to cxl_core, the > cxl_pci driver is refactored to utilize a new helper to find register > blocks by type. > > cxl_pci scanned through all register blocks and mapping the ones that > the driver will use. This logic is inverted so that the driver > specifically requests the register blocks from a new helper. Under the > hood, the same implementation of scanning through all register locator > DVSEC entries exists. > > There are 2 behavioral changes (#2 is arguable): > 1. A dev_err is introduced if cxl_map_regs fails. > 2. The previous logic would try to map component registers and device > registers multiple times if there were present and keep the mapping > of the last one found (furthest offset in the register locator). > While this is disallowed in the spec, CXL 2.0 8.1.9: "Each register > block identifier shall only occur once in the Register Locator DVSEC > structure" it was how the driver would respond to the spec violation. > The new logic will take the first found register block by type and > move on. > > Signed-off-by: Ben Widawsky <ben.widawsky@xxxxxxxxx> > > --- > Changes since v1: No changes? Luckily git am strips this section... Overall I think this refactor can be broken down further for readability and cleanup the long standing problem that the driver maps component registers for no reason. The main contributing factor to readability is that cxl_setup_pci_regs() still exists after the refactor, which also contributes to the component register problem. If the register mapping is up leveled to the caller of cxl_setup_pci_regs() (and drops mapping component registers) then a follow-on patch to rename cxl_setup_pci_regs to find_register_block becomes easier to read. Moving the cxl_register_map array out of cxl_setup_pci_regs() also makes a later patch to pass component register enumeration details to the endpoint-port that much cleaner.
