From: Naoki Yanagimoto <yanagimoto@xxxxxxxxxxxxxxxxxx>
I got a problem that an abnormal value was returned from the configuration
space of some PCIe card at hotadd. The pciehp driver regarded the function of
the device as being unavailable, so the card did not work. The problem
disappeared when I simply added 1 second wait without using DLLLA.
I think that it should wait for 1 second because "PCI Express Base
Specification Revision 3.0" says, "the software must wait for at least
1 second to judge device is broken after Data Link Layer State Changed Event".
Therefore, I send a patch that drops DLLLA checking and adds 1 second wait.
Signed-off-by: Naoki Yanagimoto <yanagimoto@xxxxxxxxxxxxxxxxxx>
---
diff -uprN -X a/Documentation/dontdiff a/drivers/pci/hotplug/pciehp_ctrl.c b/drivers/pci/hotplug/pciehp_ctrl.c
--- a/drivers/pci/hotplug/pciehp_ctrl.c 2011-06-21 12:25:46.000000000 +0900
+++ b/drivers/pci/hotplug/pciehp_ctrl.c 2011-07-04 17:36:55.000000000 +0900
@@ -206,6 +206,9 @@ static int board_added(struct slot *p_sl
if (PWR_LED(ctrl))
pciehp_green_led_blink(p_slot);
+ /* Wait for ~1 second */
+ msleep(1000);
+
/* Check link training status */
retval = pciehp_check_link_status(ctrl);
if (retval) {
diff -uprN -X a/Documentation/dontdiff a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c
--- a/drivers/pci/hotplug/pciehp_hpc.c 2011-06-21 12:25:46.000000000 +0900
+++ b/drivers/pci/hotplug/pciehp_hpc.c 2011-07-04 17:36:55.000000000 +0900
@@ -241,52 +241,11 @@ static int pcie_write_cmd(struct control
return retval;
}
-static inline int check_link_active(struct controller *ctrl)
-{
- u16 link_status;
-
- if (pciehp_readw(ctrl, PCI_EXP_LNKSTA, &link_status))
- return 0;
- return !!(link_status & PCI_EXP_LNKSTA_DLLLA);
-}
-
-static void pcie_wait_link_active(struct controller *ctrl)
-{
- int timeout = 1000;
-
- if (check_link_active(ctrl))
- return;
- while (timeout > 0) {
- msleep(10);
- timeout -= 10;
- if (check_link_active(ctrl))
- return;
- }
- ctrl_dbg(ctrl, "Data Link Layer Link Active not set in 1000 msec\n");
-}
-
int pciehp_check_link_status(struct controller *ctrl)
{
u16 lnk_status;
int retval = 0;
- /*
- * Data Link Layer Link Active Reporting must be capable for
- * hot-plug capable downstream port. But old controller might
- * not implement it. In this case, we wait for 1000 ms.
- */
- if (ctrl->link_active_reporting){
- /* Wait for Data Link Layer Link Active bit to be set */
- pcie_wait_link_active(ctrl);
- /*
- * We must wait for 100 ms after the Data Link Layer
- * Link Active bit reads 1b before initiating a
- * configuration access to the hot added device.
- */
- msleep(100);
- } else
- msleep(1000);
-
retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
if (retval) {
ctrl_err(ctrl, "Cannot read LNKSTATUS register\n");
--
Since I don't subscribe ML, please Cc me if you have any comment.
Thanks,
Naoki Yanagimoto
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