Hello Maciej,
07.09.2021 17:42, I wrote:
[ 0.625911] 8139too: 8139too Fast Ethernet driver 0.9.28
[ 0.625911] 8139too 0000:00:03.0: PCI INT A -> PIRQ 10, mask def8, excl
0000
[ 0.625911] 8139too 0000:00:03.0: PCI INT A -> newirq 11
[ 0.630068] PCI: setting IRQ 15 as level-triggered
[ 0.630068] -> edge
[ 0.630068] 8139too 0000:00:03.0: found PCI INT A -> IRQ 15
Ok, I've sorted this out. Your patch works as intended, as long as the
.link field values are encoded as numbers from 1 to 4. In the (severely
obsolete) "$IRT" routing table I discovered in my BIOS, the .link values
are some strange 0x10-0x28-0x41-0x89 numbers, whatever was the idea of
BIOS writers behind this. AFAIK such numbering is not prohibited by PCI
BIOS spec, but obviously it has to be in agreement with what register
access routines expect, or otherwise it will all break apart.
Now because this old "$IRT" table can not normally be recognized anyway,
I've converted the data to a more reasonable $PIR format, translating
0x10-0x28-0x41-0x89 numbers into 1-2-3-4 along the way, and inserted
this new table into a small unused ROM area. All looks good:
=====
[ 0.623757] 8139too: 8139too Fast Ethernet driver 0.9.28
[ 0.623757] 8139too 0000:00:03.0: PCI INT A -> PIRQ 01, mask def8,
excl 0000
[ 0.623757] 8139too 0000:00:03.0: PCI INT A -> newirq 11
[ 0.623757] PCI: setting IRQ 11 as level-triggered
=====
Dumping registers with a separate program then confirmed that settings
are correct indeed.
But I'd like to note that PIRQ values passed to pirq_finali_get/set
should better be somewhow checked for validity, as otherwise some
totally unrelated chipset registers are being unintentionally accessed.
I'm now going to test IRQ sharing.
Thank you,
Regards,
Nikolai
[ 0.630068] 8139too 0000:00:03.0: IRQ routing conflict: have IRQ 11,
want IRQ 15
[ 0.641901] 8139too 0000:00:03.0 eth0: RealTek RTL8139 at 0xc2582f00,
00:11:6b:32:85:74, IRQ 11
First, INTA is apparently routed to IRQ11 (and the network card works
just fine with that), whereas pci code wants IRQ15 for some reason.
Second, dumping chipset reg 44 shows that INTA is still set to EDGE mode
anyway, although dumping port 4D1 now shows IRQ15 was changed to LEVEL
mode, exactly as indicated in the above output. I'm not sure, but the
datasheet (page 77) seems to indicate that INTx mode set in reg 44
should match the respective IRQx mode in port 4Dx (Although the ROM BIOS
seems to only have code to change triggering mode in the 44 register and
does not care about port 4Dx whatsoever, which kinda contradicts the
datasheet)
I'll do some more digging later, but any hints are appreciated anyway.
Thank you,
Regards,
Nikolai
I'm a little busy at the moment with other stuff and may not be able to
look into it properly right now. There may be no solution, not at least
an easy one. A DMI quirk is not possible, because:
DMI not present or invalid.
There is a PCI BIOS:
PCI: PCI BIOS revision 2.10 entry at 0xf6f41, last bus=0
however, so CONFIG_PCI_BIOS just might work. Please try that too, by
choosing CONFIG_PCI_GOANY or CONFIG_PCI_GOBIOS (it may break things
horribly though I imagine).
Maciej
