Possibly update subject to be more descriptive, along lines of:
Serialize INTx masking/unmasking
On Thu, Aug 19, 2021 at 07:56:06PM +0900, Kunihiko Hayashi wrote:
> The same condition register PCI_RCV_INTX is used in irq_mask(),
> irq_unmask() and irq_ack() callbacks. Accesses to register can occur at the
> same time without lock.
> This introduces a lock into the callbacks to prevent the issue.
Rewrap into a single paragraph or add blank line between paragraphs.
s/This introduces/Add/ to make this an imperative description of what
you want this patch to do. No need for "This" since the context is
obvious.
> Fixes: 7e6d5cd88a6f ("PCI: uniphier: Add UniPhier PCIe host controller support")
> Suggested-by: Pali Rohár <pali@xxxxxxxxxx>
> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@xxxxxxxxxxxxx>
> ---
> drivers/pci/controller/dwc/pcie-uniphier.c | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c b/drivers/pci/controller/dwc/pcie-uniphier.c
> index ebe43e9..5075714 100644
> --- a/drivers/pci/controller/dwc/pcie-uniphier.c
> +++ b/drivers/pci/controller/dwc/pcie-uniphier.c
> @@ -186,12 +186,17 @@ static void uniphier_pcie_irq_ack(struct irq_data *d)
> struct pcie_port *pp = irq_data_get_irq_chip_data(d);
> struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
> + unsigned long flags;
> u32 val;
>
> + raw_spin_lock_irqsave(&pp->lock, flags);
> +
> val = readl(priv->base + PCL_RCV_INTX);
> val &= ~PCL_RCV_INTX_ALL_STATUS;
> val |= BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_STATUS_SHIFT);
> writel(val, priv->base + PCL_RCV_INTX);
> +
> + raw_spin_unlock_irqrestore(&pp->lock, flags);
> }
>
> static void uniphier_pcie_irq_mask(struct irq_data *d)
> @@ -199,12 +204,17 @@ static void uniphier_pcie_irq_mask(struct irq_data *d)
> struct pcie_port *pp = irq_data_get_irq_chip_data(d);
> struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
> + unsigned long flags;
> u32 val;
>
> + raw_spin_lock_irqsave(&pp->lock, flags);
> +
> val = readl(priv->base + PCL_RCV_INTX);
> val &= ~PCL_RCV_INTX_ALL_MASK;
> val |= BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_MASK_SHIFT);
> writel(val, priv->base + PCL_RCV_INTX);
> +
> + raw_spin_unlock_irqrestore(&pp->lock, flags);
> }
>
> static void uniphier_pcie_irq_unmask(struct irq_data *d)
> @@ -212,12 +222,17 @@ static void uniphier_pcie_irq_unmask(struct irq_data *d)
> struct pcie_port *pp = irq_data_get_irq_chip_data(d);
> struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
> + unsigned long flags;
> u32 val;
>
> + raw_spin_lock_irqsave(&pp->lock, flags);
> +
> val = readl(priv->base + PCL_RCV_INTX);
> val &= ~PCL_RCV_INTX_ALL_MASK;
> val &= ~BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_MASK_SHIFT);
> writel(val, priv->base + PCL_RCV_INTX);
> +
> + raw_spin_unlock_irqrestore(&pp->lock, flags);
> }
>
> static struct irq_chip uniphier_pcie_irq_chip = {
> --
> 2.7.4
>
