Bjorn Helgaas <helgaas@xxxxxxxxxx> writes: >> TBH I don't think of this as of a "quirk" - all systems have MRRS >> limits, it just happens that these ones have their limit lower than 4096 >> bytes. This isn't a limitation of a particular PCIe device, this is a >> common limit of the whole system. > > Do you have a reference for this? I don't see anything in the PCIe > spec that suggests platforms must limit MRRS, and it seems that only > these ARM-related controllers have this issue. I meant there is always a limit - isn't Max_Read_Request_Size a limit? Device Control Register (Offset 08h) Bit Location 14:12 Max_Read_Request_Size allows for max 4096 bytes, though two values are reserved, so there is room for some easy extension. - non-ARM (non-DWC?) systems are limited to 4096 bytes - DWC-based systems are limited to 128, 256, 512 bytes (are there 4096-byte ones?) That's how I understand it, please correct me if I'm wrong. -- Krzysztof "Chris" Hałasa Sieć Badawcza Łukasiewicz Przemysłowy Instytut Automatyki i Pomiarów PIAP Al. Jerozolimskie 202, 02-486 Warszawa
