Experiments showed that in register PCIE_MSI_PAYLOAD_REG is stored number
of the last received MSI interrupt and not number of MSI interrupt which
belongs to msi_idx bit. Therefore this implies that aardvark HW can cache
only bits [4:0] of received MSI interrupts with effectively means that it
supports only MSI interrupts with numbers 0-31.
Do not read PCIE_MSI_PAYLOAD_REG register for determining MSI interrupt
number. Instead ensure that pci-aardvark.c configures only MSI numbers in
range 0-31 and then msi_idx contains correct received MSI number.
Signed-off-by: Pali Rohár <pali@xxxxxxxxxx>
Cc: stable@xxxxxxxxxxxxxxx
---
drivers/pci/controller/pci-aardvark.c | 11 +++--------
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
index 5e4febdbdd33..bacfccee44fe 100644
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -1199,7 +1199,6 @@ static void advk_pcie_remove_irq_domain(struct advk_pcie *pcie)
static void advk_pcie_handle_msi(struct advk_pcie *pcie)
{
u32 msi_val, msi_mask, msi_status, msi_idx;
- u16 msi_data;
int virq;
msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG);
@@ -1210,17 +1209,13 @@ static void advk_pcie_handle_msi(struct advk_pcie *pcie)
if (!(BIT(msi_idx) & msi_status))
continue;
- /*
- * msi_idx contains bits [4:0] of the msi_data and msi_data
- * contains 16bit MSI interrupt number from MSI inner domain
- */
advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG);
- msi_data = advk_readl(pcie, PCIE_MSI_PAYLOAD_REG) & PCIE_MSI_DATA_MASK;
- virq = irq_find_mapping(pcie->msi_inner_domain, msi_data);
+
+ virq = irq_find_mapping(pcie->msi_inner_domain, msi_idx);
if (virq)
generic_handle_irq(virq);
else
- dev_err_ratelimited(&pcie->pdev->dev, "unexpected MSI 0x%04hx\n", msi_data);
+ dev_err_ratelimited(&pcie->pdev->dev, "unexpected MSI 0x%02x\n", msi_idx);
}
advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING,
--
2.20.1
