DWC PCIe controller imposes limits on the Read Request Size that it can handle. For i.MX6 family it's fixed at 512 bytes by default. If a memory read larger than the limit is requested, the CPU responds with Completer Abort (CA) (on i.MX6 Unsupported Request (UR) is returned instead due to a design error). The i.MX6 documentation states that the limit can be changed by writing to the PCIE_PL_MRCCR0 register, however there is a fixed (and undocumented) maximum (CX_REMOTE_RD_REQ_SIZE constant). Tests indicate that values larger than 512 bytes don't work, though. This patch makes the RTL8111 work on i.MX6. Signed-off-by: Krzysztof Hałasa <khalasa@xxxxxxx> diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 0c473d75e625..a11ec93a8cd0 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -34,6 +34,9 @@ config PCI_DOMAINS_GENERIC config PCI_SYSCALL bool +config NEED_PCIE_MAX_MRRS + bool + source "drivers/pci/pcie/Kconfig" config PCI_MSI diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index 423d35872ce4..b59a4c91cb3b 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -98,6 +98,7 @@ config PCI_IMX6 depends on ARCH_MXC || COMPILE_TEST depends on PCI_MSI_IRQ_DOMAIN select PCIE_DW_HOST + select NEED_PCIE_MAX_MRRS config PCIE_SPEAR13XX bool "STMicroelectronics SPEAr PCIe controller" diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 80fc98acf097..7a83f677a632 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -1148,6 +1148,7 @@ static int imx6_pcie_probe(struct platform_device *pdev) imx6_pcie->vph = NULL; } + max_pcie_mrrs = 512; platform_set_drvdata(pdev, imx6_pcie); ret = imx6_pcie_attach_pd(dev); diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index aacf575c15cf..8ed8d2e75f4c 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -112,6 +112,10 @@ enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PEER2PEER; enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT; #endif +#ifdef CONFIG_NEED_PCIE_MAX_MRRS +u16 max_pcie_mrrs = 4096; // no limit +#endif + /* * The default CLS is used if arch didn't set CLS explicitly and not * all pci devices agree on the same value. Arch can override either @@ -5816,6 +5820,11 @@ int pcie_set_readrq(struct pci_dev *dev, int rq) rq = mps; } +#ifdef CONFIG_NEED_PCIE_MAX_MRRS + if (rq > max_pcie_mrrs) + rq = max_pcie_mrrs; +#endif + v = (ffs(rq) - 8) << 12; ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, diff --git a/include/linux/pci.h b/include/linux/pci.h index 540b377ca8f6..7368be024c31 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -994,6 +994,7 @@ enum pcie_bus_config_types { }; extern enum pcie_bus_config_types pcie_bus_config; +extern u16 max_pcie_mrrs; extern struct bus_type pci_bus_type; -- Krzysztof "Chris" Hałasa Sieć Badawcza Łukasiewicz Przemysłowy Instytut Automatyki i Pomiarów PIAP Al. Jerozolimskie 202, 02-486 Warszawa