On Tue, 2011-06-14 at 07:54 +0200, Rolf Eike Beer wrote: > Jon Mason wrote: > > There is a sizable performance boost for having the largest possible > > maximum payload size on each PCI-E device. However, the maximum payload > > size must be uniform on a given PCI-E fabric, and each device, bridge, > > and root port can have a different max size. To find and configure the > > optimal MPS settings, one must walk the fabric and determine the largest > > MPS available on all the devices on the given fabric. > > So you are basically telling me that if I have one device that only can do 128 > byte no other device can do more? Even if I don't do device2device transfers? > That's odd. Not only have I worked with such configurations on many boards for > years, but it basically renders that totally useless as all motherboards I got > my fingers on have on-chip devices that only support 128 bytes. > > Or did you mean this must be uniform on one bus (since every physical slot has > usually it's own bus)? Well, it's a bit in-between, which is what I've been talking about in my emails. It really all depends on those two points: - Do you ever want to do device-device DMA ? If yes, you need to take it into account and thus the max payload of both devices and all bridges in between must be the minimum of the support along the path. - Can your PHB (PCIe Host bridge) generate very large requests (as a result of using some kind of DMA engine for example. In that case, you need to either clamp the PHB globally (ouch) or ensure that whoever uses said DMA engine knows the limitations of the target device. Appart from that, it's all about DMA from what I can tell, and so we only need to make sure that devices are clamped to the capabilities of their parent, -not- the other way around. IE. You want to make sure that a device doesn't issue DMA TLPs larger than the bridge above it can cope with. So the algorithm used by our firmware is to start at the top of the tree with the max size supported by the PHB, and set things that way, going down, clamping the size as we hit a bridge that has limitations. Such a setup means only the hotplug device itself needs to be limited to the capabilities of the bridge above it, and not everything else. Cheers, Ben. > > + if (dev->is_hotplug_bridge) > > + smpss = 0; > > + > > + if (*smpss > dev->pcie_mpss) > > + *smpss = dev->pcie_mpss; > > + } > > The first one is wrong. It must be either "*smpss = 0". How it currently is you > only crash the machine with a NULL deref. > > Eike -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
