On Wed, Jul 21, 2021 at 10:39:11AM +0200, Mauro Carvalho Chehab wrote: > Convert the file into a JSON description at the yaml format. And add 970... > > Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@xxxxxxxxxx> > --- > .../bindings/pci/hisilicon,kirin-pcie.yaml | 87 +++++++++++++++++++ > .../devicetree/bindings/pci/kirin-pcie.txt | 50 ----------- > .../devicetree/bindings/pci/snps,dw-pcie.yaml | 2 +- > MAINTAINERS | 2 +- > 4 files changed, 89 insertions(+), 52 deletions(-) > create mode 100644 Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml > delete mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txt > > diff --git a/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml > new file mode 100644 > index 000000000000..eabc651c9766 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml > @@ -0,0 +1,87 @@ > +# SPDX-License-Identifier: GPL-2.0 > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pci/hisilicon,kirin-pcie.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: HiSilicon Kirin SoCs PCIe host DT description > + > +maintainers: > + - Xiaowei Song <songxiaowei@xxxxxxxxxxxxx> > + - Binghui Wang <wangbinghui@xxxxxxxxxxxxx> > + > +description: | > + Kirin PCIe host controller is based on the Synopsys DesignWare PCI core. > + It shares common functions with the PCIe DesignWare core driver and > + inherits common properties defined in > + Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml. > + > +allOf: > + - $ref: /schemas/pci/snps,dw-pcie.yaml# > + > +properties: > + compatible: > + contains: > + enum: > + - hisilicon,kirin960-pcie > + - hisilicon,kirin970-pcie > + > + reg: > + description: | > + Should contain rc_dbi, apb, config registers location and length. > + minItems: 3 > + maxItems: 4 > + > + reg-names: > + items: > + - const: dbi # controller configuration registers > + - const: apb # apb Ctrl register defined by Kirin > + - const: config # PCIe configuration space registers > + - const: phy # apb PHY register used on Kirin 960 PHY > + minItems: 3 > + maxItems: 4 > + > + reset-gpios: > + description: The GPIO(s) to generate PCIe PERST# assert and deassert signal. > + minItems: 1 > + maxItems: 4 I'll apply this, but only with 'maxItems: 1' if you want to separate the discussion on that part. > + > +required: > + - compatible > + - reg > + - reg-names > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + pcie: pcie@f4000000 { > + compatible = "hisilicon,kirin970-pcie"; > + reg = <0x0 0xf4000000 0x0 0x1000>, > + <0x0 0xff3fe000 0x0 0x1000>, > + <0x0 0xf4000000 0 0x2000>; > + reg-names = "dbi", "apb", "config"; > + bus-range = <0x0 0x1>; > + #address-cells = <3>; > + #size-cells = <2>; > + device_type = "pci"; > + ranges = <0x02000000 0x0 0x00000000 0x0 0xf5000000 0x0 0x2000000>; > + num-lanes = <1>; > + #interrupt-cells = <1>; > + interrupts = <0 283 4>; > + interrupt-names = "msi"; > + interrupt-map-mask = <0xf800 0 0 7>; > + interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, > + <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, > + <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, > + <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; > + reset-gpios = <&gpio7 0 0 >, <&gpio25 2 0 >, > + <&gpio3 1 0 >, <&gpio27 4 0 >; > + }; > + };
