Re: [PATCH v3] PCI: Max Payload Size BIOS workaround

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On Fri, 2011-06-03 at 11:00 -0500, Jon Mason wrote:
> 
> You are correct.  I was only thinking about the DMA write.  The entire
> fabric needs have each device/bridge MPS set to the smallest MPS
> found, otherwise DMA reads could be too large for a device on the
> fabric and cause an PCI unrecoverable error.
> 
> So the correct solution is to find the smallest MPS per fabric while
> walking the bus, then walk the bus again setting each device/bridge's
> MPS to the smallest MPS found.
> 
> This patch just got much more complicated.  Damn you crappy BIOS
> developers!

Same with max read req. size except that for that one we don't even have
a register telling us what the bridge max is in the first place.

I have some in-house code to fix that up on powerpc at boot that I
haven't released yet (for a platform that we haven't published yet) but
it's only boot time, I haven't dealt with the hotplug case.

The problem I see with hotplug is that potentially, one could have to
change the entire hierarchy below the PHB when a new device is plugged
with a smaller max payload size than what was used before.

However, I didn't think it was "safe" to just change the size on a live
system, devices have to be quiescent.

That makes it impossible to do reliably in my book, ie, anything with a
hotplug might have to be hard wired to the smallest size unless the
hotplug happens at the PHB level in which case there is no risk of
disrupting another device while changing the size.

Ben.


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