On Tue, Jul 06, 2021 at 05:15:02PM -0500, stuart hayes wrote: > I believe the Link Down is happening because a hot reset is propagated down > when the link is lost under the root port 64:02.0. From the PCIe Base Spec > 5.0, section 6.6.1 "conventional reset": [...] Hm, sounds plausible. Just so that I understand this correctly, the hotplug port at 0000:68:00.0 is DPC-capable, but the error that is contained by DPC at the Root Port occurs further up in the hierarchy, right? (I.e. somewhere above the hotplug port.) The patch you're using to work around the issue would break if the hotplug port is *not* DPC-capable. Yes, yes, I understand that it's not meant as a real patch, but it shows how tricky it is to fix the issue. I need to do a little more thinking what a proper solution could look like. Thanks, Lukas
