Dear all, I'm trying to read a memory mapped register in a PCIe peripheral. If that peripheral is busy doing any kind of work and cannot receive the Memory Read Request from the CPU, what is it likely to happen? That packet is buffered at level 2 in that peripheral, but the TLP is not processed and not answered. I mean that a read operation of a PCI memory mapped address is supposed to be atomic from the CPU point of view. Am I correct? Then, if that atomic operation cannot end, will system crash? In my concrete scenario, I have a FPGA with a PCIe endpoint attacched to a x86 system. That FPGA is receiving lots of TLPs because of a Downlink DMA transfer. Buffers in that FPGA get full, and then FPGA stops receiving any more TLPs (of any kind) until that buffer has some free space again. When that FPGA stops receiving TLPs, I send a Memory Read Request from the x86 CPU in order to, for example, read one status register. In this scenario, FPGA will not be able to proccess that TLP (and consequently answer that request). And remembering my thought about a Memory Read Request from the cpu to be atomic... I suppose this is an awful scenario, isn't it? In this concrete scenario, my Linux system goes down without any log messages, it is a quick and quiet death. Is this the expected behaviour for you? Could you please give me any hints, any ideas about how to work around this situation? Or about how can I debug further? Does the linux Kernel have any debug compilation-time-option for this kind of PCI problems? Thanks very much in advance. Regards, Ricardo -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
