On Fri, Jul 02, 2021 at 05:39:43PM +0200, Ben Hutchings wrote:
> On Thu, 2021-07-01 at 10:25 -0500, Bjorn Helgaas wrote:
> [...]
> > After 27d868b5e6cfa, pci_configure_device() did actually call
> > pcie_set_mps(), which updates the Device Control register (possibly
> > restricted by dev->pcie_mpss, which is set by this quirk).
> >
> > The fixup_mpss_256() quirk was added in 2011 by a94d072b2023 ("PCI:
> > Add quirk for known incorrect MPSS"). Interesting that 27d868b5e6cfa
> > was merged in 2015 but apparently nobody noticed until now. I guess
> > those Solarflare devices aren't widely used?
> [...]
>
> The key thing is that this quirk was working around an issue with
> legacy interrupts, while the sfc and sfc-falcon drivers have always
> preferred to use MSIs if available. (But I also don't think many
> SFC4000-based NICs were sold, and they were EOL'd about 10 years ago.)
Just out of curiosity, do you happen to remember the legacy interrupt
connection? MPS has to do with the maximum TLP size, and it's not
obvious to me why using INTx vs MSI would matter there.
I guessing the scenario is that SFC4000 uses either either INTx or
MSI to signal some kind of I/O completion, the ISR puts more I/Os in
the queue, the SFC4000 does a DMA read, and chokes on a Completion TLP
that's too big? But somehow if it uses MSI, it can handle bigger
TLPS?
Not a big deal; I think it's obvious that we need Marek's patch to fix
the ordering issue.
Bjorn
