Hi,
在 2021/6/24 16:23, Pali Rohár 写道:
On Thursday 24 June 2021 10:08:54 xxm wrote:
在 2021/6/23 22:33, Lorenzo Pieralisi 写道:
On Thu, May 06, 2021 at 10:35:44AM +0800, Simon Xue wrote:
+static int rockchip_pcie_start_link(struct dw_pcie *pci)
+{
+ struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
+
+ /* Reset device */
+ gpiod_set_value_cansleep(rockchip->rst_gpio, 0);
+
+ rockchip_pcie_enable_ltssm(rockchip);
+
+ /*
+ * PCIe requires the refclk to be stable for 100µs prior to releasing
+ * PERST. See table 2-4 in section 2.6.2 AC Specifications of the PCI
+ * Express Card Electromechanical Specification, 1.1. However, we don't
+ * know if the refclk is coming from RC's PHY or external OSC. If it's
+ * from RC, so enabling LTSSM is the just right place to release #PERST.
+ * We need more extra time as before, rather than setting just
+ * 100us as we don't know how long should the device need to reset.
+ */
+ msleep(100);
Any rationale behind the time chosen ?
We found some device need about 30ms, so 100ms here just leave more room for
other devices.
Can you share information which PCIe card needs 30ms?
Last year I did tests with more WiFi AC cards and "the slowest" one was
Compex WLE1216 which needed about 11ms (more than 10ms). All other cards
were happy with just 1-2ms.
Sorry, it was about 5 years ago, I can't find the specific card now.
By the way, we also take other's upstream code "msleep(100)" as a reference.
