On Mon, Jun 7, 2021 at 1:47 AM <srikanth.thokala@xxxxxxxxx> wrote: > > From: Srikanth Thokala <srikanth.thokala@xxxxxxxxx> > > Add driver for Intel Keem Bay SoC PCIe controller. This controller > is based on DesignWare PCIe core. > > In Root Complex mode, only internal reference clock is possible for > Keem Bay A0. For Keem Bay B0, external reference clock can be used > and will be the default configuration. Currently, keembay_pcie_of_data > structure has one member. It will be expanded later to handle this > difference. > > Endpoint mode link initialization is handled by the boot firmware. > > Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@xxxxxxxxx> > Acked-by: Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx> > Signed-off-by: Srikanth Thokala <srikanth.thokala@xxxxxxxxx> > Reviewed-by: Krzysztof Wilczyński <kw@xxxxxxxxx> > --- > MAINTAINERS | 7 + > drivers/pci/controller/dwc/Kconfig | 28 ++ > drivers/pci/controller/dwc/Makefile | 1 + > drivers/pci/controller/dwc/pcie-keembay.c | 451 ++++++++++++++++++++++ > 4 files changed, 487 insertions(+) > create mode 100644 drivers/pci/controller/dwc/pcie-keembay.c Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
