On Sat, 5 Jun 2021 23:05:22 -0700
Dan Williams <dan.j.williams@xxxxxxxxx> wrote:
> While the resources enumerated by the CEDT.CFMWS identify a cxl_port
> with host bridges as downstream ports, host bridges themselves are
> upstream ports that decode to downstream ports represented by PCIe Root
> Ports. Walk the PCIe Root Ports connected to a CXL Host Bridge,
> identified by the ACPI0016 _HID, and add each one as a cxl_dport of the
> host bridge cxl_port.
>
> For now, component registers are not enumerated, only the first order
> uport / dport relationships.
>
> Signed-off-by: Dan Williams <dan.j.williams@xxxxxxxxx>
LGTM
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx>
> ---
> drivers/cxl/acpi.c | 97 +++++++++++++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 95 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c
> index 0ae7464b603d..ec324bf063b8 100644
> --- a/drivers/cxl/acpi.c
> +++ b/drivers/cxl/acpi.c
> @@ -8,6 +8,48 @@
> #include <linux/pci.h>
> #include "cxl.h"
>
> +struct cxl_walk_context {
> + struct device *dev;
> + struct pci_bus *root;
> + struct cxl_port *port;
> + int error;
> + int count;
> +};
> +
> +static int match_add_root_ports(struct pci_dev *pdev, void *data)
> +{
> + struct cxl_walk_context *ctx = data;
> + struct pci_bus *root_bus = ctx->root;
> + struct cxl_port *port = ctx->port;
> + int type = pci_pcie_type(pdev);
> + struct device *dev = ctx->dev;
> + u32 lnkcap, port_num;
> + int rc;
> +
> + if (pdev->bus != root_bus)
> + return 0;
> + if (!pci_is_pcie(pdev))
> + return 0;
> + if (type != PCI_EXP_TYPE_ROOT_PORT)
> + return 0;
> + if (pci_read_config_dword(pdev, pci_pcie_cap(pdev) + PCI_EXP_LNKCAP,
> + &lnkcap) != PCIBIOS_SUCCESSFUL)
> + return 0;
> +
> + /* TODO walk DVSEC to find component register base */
> + port_num = FIELD_GET(PCI_EXP_LNKCAP_PN, lnkcap);
> + rc = cxl_add_dport(port, &pdev->dev, port_num, CXL_RESOURCE_NONE);
> + if (rc) {
> + ctx->error = rc;
> + return rc;
> + }
> + ctx->count++;
> +
> + dev_dbg(dev, "add dport%d: %s\n", port_num, dev_name(&pdev->dev));
> +
> + return 0;
> +}
> +
> static struct acpi_device *to_cxl_host_bridge(struct device *dev)
> {
> struct acpi_device *adev = to_acpi_device(dev);
> @@ -17,6 +59,44 @@ static struct acpi_device *to_cxl_host_bridge(struct device *dev)
> return NULL;
> }
>
> +/*
> + * A host bridge is a dport to a CFMWS decode and it is a uport to the
> + * dport (PCIe Root Ports) in the host bridge.
> + */
> +static int add_host_bridge_uport(struct device *match, void *arg)
> +{
> + struct acpi_device *bridge = to_cxl_host_bridge(match);
> + struct cxl_port *root_port = arg;
> + struct device *host = root_port->dev.parent;
> + struct acpi_pci_root *pci_root;
> + struct cxl_walk_context ctx;
> + struct cxl_port *port;
> +
> + if (!bridge)
> + return 0;
> +
> + pci_root = acpi_pci_find_root(bridge->handle);
> + if (!pci_root)
> + return -ENXIO;
> +
> + /* TODO: fold in CEDT.CHBS retrieval */
> + port = devm_cxl_add_port(host, match, CXL_RESOURCE_NONE, root_port);
> + if (IS_ERR(port))
> + return PTR_ERR(port);
> + dev_dbg(host, "%s: add: %s\n", dev_name(match), dev_name(&port->dev));
> +
> + ctx = (struct cxl_walk_context){
> + .dev = host,
> + .root = pci_root->bus,
> + .port = port,
> + };
> + pci_walk_bus(pci_root->bus, match_add_root_ports, &ctx);
> +
> + if (ctx.count == 0)
> + return -ENODEV;
> + return ctx.error;
> +}
> +
> static int add_host_bridge_dport(struct device *match, void *arg)
> {
> int rc;
> @@ -49,6 +129,7 @@ static int add_host_bridge_dport(struct device *match, void *arg)
>
> static int cxl_acpi_probe(struct platform_device *pdev)
> {
> + int rc;
> struct cxl_port *root_port;
> struct device *host = &pdev->dev;
> struct acpi_device *adev = ACPI_COMPANION(host);
> @@ -58,8 +139,20 @@ static int cxl_acpi_probe(struct platform_device *pdev)
> return PTR_ERR(root_port);
> dev_dbg(host, "add: %s\n", dev_name(&root_port->dev));
>
> - return bus_for_each_dev(adev->dev.bus, NULL, root_port,
> - add_host_bridge_dport);
> + rc = bus_for_each_dev(adev->dev.bus, NULL, root_port,
> + add_host_bridge_dport);
> + if (rc)
> + return rc;
> +
> + /*
> + * Root level scanned with host-bridge as dports, now scan host-bridges
> + * for their role as CXL uports to their CXL-capable PCIe Root Ports.
> + */
> + rc = bus_for_each_dev(adev->dev.bus, NULL, root_port,
> + add_host_bridge_uport);
> + if (rc)
> + dev_err(host, "failed to scan host bridges\n");
> + return 0;
> }
>
> static const struct acpi_device_id cxl_acpi_ids[] = {
>
