在 2021/5/19 10:26, Huacai Chen 写道:
Hi, Bjorn,
On Tue, May 18, 2021 at 9:59 PM Bjorn Helgaas <helgaas@xxxxxxxxxx> wrote:
[+cc Rob, beginning of thread
https://lore.kernel.org/r/20210514080025.1828197-5-chenhuacai@xxxxxxxxxxx]
On Sat, May 15, 2021 at 11:52:53AM +0800, Huacai Chen wrote:
On Fri, May 14, 2021 at 10:52 PM Jiaxun Yang <jiaxun.yang@xxxxxxxxxxx> wrote:
在 2021/5/14 16:00, Huacai Chen 写道:
From: Jianmin Lv <lvjianmin@xxxxxxxxxxx>
In LS7A, multifunction device use same pci PIN and different
irq for different function, so fix it for standard pci PIN
usage.
Hmm, I'm unsure about this change.
The PCIe port, or PCI-to-PCI bridge on LS7A only have a single
upstream interrupt specified in DeviceTree, how can this quirk
work?
LS7A will be shared by MIPS-based Loongson and LoongArch-based
Loongson, LoongArch use ACPI rather than FDT, so this quirk is needed.
Can you expand on this a little bit?
Which DT binding are you referring to? Is it in the Linux source
tree?
I referring to arch/mips/boot/dts/loongson/ls7a-pch.dtsi, it is
already in Linux source tree.
I think Linux reads Interrupt Pin for both FDT and ACPI systems, and
apparently that register contains the same value for all functions of
this multi-function device.
The quirk will be applied for both FDT and ACPI systems, but it sounds
like you're saying this is needed *because* LoongArch uses ACPI.
Jiaxun said that FDT system doesn't need this quirk, maybe he know more.
For FDT system, the IRQ routine of PCI ports looks like:
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &pic 41 IRQ_TYPE_LEVEL_HIGH>;
It means they are all going to the same parent IRQ no matter what we read
from pin register. And it's the actual hardware behavior AFAIK.
Thanks.
- Jiaxun
Huacai
Bjorn
