Hi Linus, I love your patch! Yet something to improve: [auto build test ERROR on soc/for-next] [also build test ERROR on pci/next block/for-next linus/master v5.12 next-20210503] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Linus-Walleij/IXP4xx-PCI-rework/20210504-051847 base: https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git for-next config: ia64-allmodconfig (attached as .config) compiler: ia64-linux-gcc (GCC) 9.3.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/0day-ci/linux/commit/f3c7dd73e6c1b358e1f61a4b3a186ce5b336deaf git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Linus-Walleij/IXP4xx-PCI-rework/20210504-051847 git checkout f3c7dd73e6c1b358e1f61a4b3a186ce5b336deaf # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross W=1 ARCH=ia64 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp@xxxxxxxxx> All errors (new ones prefixed by >>): drivers/pci/controller/pci-ixp4xx.c: In function 'ixp4xx_pci_abort_handler': >> drivers/pci/controller/pci-ixp4xx.c:513:7: error: 'struct pt_regs' has no member named 'ARM_pc' 513 | regs->ARM_pc += 4; | ^~ drivers/pci/controller/pci-ixp4xx.c: In function 'ixp4xx_pci_probe': >> drivers/pci/controller/pci-ixp4xx.c:566:2: error: implicit declaration of function 'hook_fault_code' [-Werror=implicit-function-declaration] 566 | hook_fault_code(16+6, ixp4xx_pci_abort_handler, SIGBUS, 0, | ^~~~~~~~~~~~~~~ cc1: some warnings being treated as errors Kconfig warnings: (for reference only) WARNING: unmet direct dependencies detected for FRAME_POINTER Depends on DEBUG_KERNEL && (M68K || UML || SUPERH) || ARCH_WANT_FRAME_POINTERS Selected by - FAULT_INJECTION_STACKTRACE_FILTER && FAULT_INJECTION_DEBUG_FS && STACKTRACE_SUPPORT && !X86_64 && !MIPS && !PPC && !S390 && !MICROBLAZE && !ARM && !ARC && !X86 vim +513 drivers/pci/controller/pci-ixp4xx.c 481 482 static int ixp4xx_pci_abort_handler(unsigned long addr, unsigned int fsr, 483 struct pt_regs *regs) 484 { 485 struct ixp4xx_pci *p = ixp4xx_pci_abort_singleton; 486 u32 isr, status; 487 int ret; 488 489 isr = __raw_readl(p->base + IXP4XX_PCI_ISR); 490 ret = ixp4xx_crp_read_config(p, PCI_STATUS, 2, &status); 491 if (ret) { 492 dev_err(p->dev, "unable to read abort status\n"); 493 return -EINVAL; 494 } 495 496 dev_err(p->dev, 497 "PCI: abort_handler addr = %#lx, isr = %#x, status = %#x\n", 498 addr, isr, status); 499 500 /* Make sure the Master Abort bit is reset */ 501 __raw_writel(IXP4XX_PCI_ISR_PFE, p->base + IXP4XX_PCI_ISR); 502 status |= PCI_STATUS_REC_MASTER_ABORT; 503 ret = ixp4xx_crp_write_config(p, PCI_STATUS, 2, status); 504 if (ret) 505 dev_err(p->dev, "unable to clear abort status bit\n"); 506 507 /* 508 * If it was an imprecise abort, then we need to correct the 509 * return address to be _after_ the instruction. 510 */ 511 if (fsr & (1 << 10)) { 512 dev_err(p->dev, "imprecise abort\n"); > 513 regs->ARM_pc += 4; 514 } 515 516 return 0; 517 } 518 519 static int ixp4xx_pci_probe(struct platform_device *pdev) 520 { 521 struct device *dev = &pdev->dev; 522 struct device_node *np = dev->of_node; 523 struct ixp4xx_pci *p; 524 struct pci_host_bridge *host; 525 int ret; 526 u32 val; 527 phys_addr_t addr; 528 u32 basereg[4] = { 529 PCI_BASE_ADDRESS_0, 530 PCI_BASE_ADDRESS_1, 531 PCI_BASE_ADDRESS_2, 532 PCI_BASE_ADDRESS_3, 533 }; 534 int i; 535 536 host = devm_pci_alloc_host_bridge(dev, sizeof(*p)); 537 if (!host) 538 return -ENOMEM; 539 540 host->ops = &ixp4xx_pci_ops; 541 p = pci_host_bridge_priv(host); 542 host->sysdata = p; 543 p->dev = dev; 544 raw_spin_lock_init(&p->lock); 545 546 /* 547 * Set up quirk for erratic behaviour in the 42x variant 548 * when accessing config space. 549 */ 550 if (of_device_is_compatible(np, "intel,ixp42x-pci")) { 551 p->errata_hammer = true; 552 dev_info(dev, "activate hammering errata\n"); 553 } 554 555 p->base = devm_platform_ioremap_resource(pdev, 0); 556 if (IS_ERR(p->base)) 557 return PTR_ERR(p->base); 558 559 val = __raw_readl(p->base + IXP4XX_PCI_CSR); 560 p->host_mode = !!(val & IXP4XX_PCI_CSR_HOST); 561 dev_info(dev, "controller is in %s mode\n", 562 p->host_mode ? "host" : "option"); 563 564 /* Hook in our fault handler for PCI errors */ 565 ixp4xx_pci_abort_singleton = p; > 566 hook_fault_code(16+6, ixp4xx_pci_abort_handler, SIGBUS, 0, 567 "imprecise external abort"); 568 569 ret = ixp4xx_pci_parse_map_ranges(p); 570 if (ret) 571 return ret; 572 573 ret = ixp4xx_pci_parse_map_dma_ranges(p); 574 if (ret) 575 return ret; 576 577 /* This is only configured in host mode */ 578 if (p->host_mode) { 579 addr = __pa(PAGE_OFFSET); 580 /* This is a noop (0x00) but explains what is going on */ 581 addr |= PCI_BASE_ADDRESS_SPACE_MEMORY; 582 583 for (i = 0; i < 4; i++) { 584 /* Write this directly into the config space */ 585 ret = ixp4xx_crp_write_config(p, basereg[i], 4, addr); 586 if (ret) 587 dev_err(dev, "failed to set up PCI_BASE_ADDRESS_%d\n", i); 588 else 589 dev_info(dev, "set PCI_BASE_ADDR_%d to %pa\n", i, &addr); 590 addr += SZ_16M; 591 } 592 593 /* 594 * Enable CSR window at 64 MiB to allow PCI masters to continue 595 * prefetching past the 64 MiB boundary, if all AHB to PCI windows 596 * are consecutive. 597 */ 598 ret = ixp4xx_crp_write_config(p, PCI_BASE_ADDRESS_4, 4, addr); 599 if (ret) 600 dev_err(dev, "failed to set up PCI_BASE_ADDRESS_4\n"); 601 else 602 dev_info(dev, "set PCI_BASE_ADDR_4 to %pa\n", &addr); 603 604 /* 605 * Put the IO memory at the very end of physical memory at 606 * 0xfffffc00. This is when the PCI is trying to access IO 607 * memory over AHB. 608 */ 609 addr = 0xfffffc00; 610 addr |= PCI_BASE_ADDRESS_SPACE_IO; 611 ret = ixp4xx_crp_write_config(p, PCI_BASE_ADDRESS_5, 4, addr); 612 if (ret) 613 dev_err(dev, "failed to set up PCI_BASE_ADDRESS_5\n"); 614 else 615 dev_info(dev, "set PCI_BASE_ADDR_5 to %pa\n", &addr); 616 617 /* 618 * Retry timeout to 0x80 619 * Transfer ready timeout to 0xff 620 */ 621 ret = ixp4xx_crp_write_config(p, IXP4XX_PCI_RTOTTO, 4, 622 0x000080ff); 623 if (ret) 624 dev_err(dev, "failed to set up TRDY limit\n"); 625 else 626 dev_info(dev, "set TRDY limit to 0x80ff\n"); 627 } 628 629 /* Clear interrupts */ 630 val = IXP4XX_PCI_ISR_PSE | IXP4XX_PCI_ISR_PFE | IXP4XX_PCI_ISR_PPE | IXP4XX_PCI_ISR_AHBE; 631 __raw_writel(val, p->base + IXP4XX_PCI_ISR); 632 633 /* 634 * Set Initialize Complete in PCI Control Register: allow IXP4XX to 635 * respond to PCI configuration cycles. Specify that the AHB bus is 636 * operating in big endian mode. Set up byte lane swapping between 637 * little-endian PCI and the big-endian AHB bus. 638 */ 639 val = IXP4XX_PCI_CSR_IC | IXP4XX_PCI_CSR_ABE; 640 #ifdef __ARMEB__ 641 val |= (IXP4XX_PCI_CSR_PDS | IXP4XX_PCI_CSR_ADS); 642 #endif 643 __raw_writel(val, p->base + IXP4XX_PCI_CSR); 644 645 646 ret = ixp4xx_crp_write_config(p, PCI_COMMAND, 2, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); 647 if (ret) 648 dev_err(dev, "unable to initialize master and command memory\n"); 649 else 650 dev_info(dev, "initialized as master\n"); 651 652 ret = pci_scan_root_bus_bridge(host); 653 if (ret) { 654 dev_err(dev, "failed to scan host: %d\n", ret); 655 return ret; 656 } 657 658 p->bus = host->bus; 659 660 pci_bus_assign_resources(p->bus); 661 pci_bus_add_devices(p->bus); 662 663 return 0; 664 } 665 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@xxxxxxxxxxxx
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