On Fri, Apr 30, 2021 at 3:10 AM Thomas Gleixner <tglx@xxxxxxxxxxxxx> wrote: > > Nitesh, > > On Thu, Apr 29 2021 at 17:44, Nitesh Lal wrote: > > First of all: Nice analysis, well done! Thanks, Thomas. > > > So to understand further what the problem was with the older kernel based > > on Jesse's description and whether it is still there I did some more > > digging. Following are some of the findings (kindly correct me if > > there is a gap in my understanding): <snip> > > > > I think this explains why even if we have multiple CPUs in the SMP affinity > > mask the interrupts may only land on CPU0. > > There are two issues in the pre rework vector management: > > 1) The allocation logic itself which preferred lower numbered CPUs and > did not try to spread out the vectors accross CPUs. This was pretty > much true for any APIC addressing mode. > > 2) The multi CPU affinity support if supported by the APIC > mode. That's restricted to logical APIC addressing mode. That is > available for non X2APIC up to 8 CPUs and with X2APIC it requires > to be in cluster mode. > > All other addressing modes had a single CPU target selected under > the hood which due to #1 was ending up on CPU0 most of the time at > least up to the point where it still had vectors available. > > Also logical addressing mode with multiple target CPUs was subject > to #1 and due to the delivery logic the lowest numbered CPU (APIC) > was where most interrupts ended up. > Right, thank you for confirming. Based on this analysis and the fact that with your re-work the interrupts seems to be naturally spread across the CPUs, will it be safe to revert Jesse's patch e2e64a932 genirq: Set initial affinity in irq_set_affinity_hint() as it overwrites the previously set IRQ affinity mask for some of the devices? IMHO if we think that this patch is still solving some issue other than what Jesse has mentioned then perhaps we should reproduce that and fix it directly from the request_irq code path. -- Nitesh
