On Tuesday 30 March 2021 15:04:02 Maciej W. Rozycki wrote: > On Thu, 25 Mar 2021, David Laight wrote: > > > I can't see the value in the (nice bound) copy of the PCI 2.0 spec I have. > > But IIRC it is 100ms (it might just me 500ms). > > While this might seem like ages it can be problematic if targets have > > to load large FPGA images from serial EEPROMs. > > AFAICT it is 100ms for the Conventional Reset before Configuration > Requests are allowed to be issued in the first place... Hi Maciej! Now I see that we have talked about two different things. My question is: How long should be card is reset state. And you described timeouts after reset finish... which are different timeouts. In case you know also timeout how long should card stay in reset state then please let us know!
