On Tue, Apr 6, 2021 at 10:47 AM Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx> wrote: > > On Thu, 1 Apr 2021 07:31:03 -0700 > Dan Williams <dan.j.williams@xxxxxxxxx> wrote: > > > While CXL Memory Device endpoints locate the CXL MMIO registers in a PCI > > BAR, CXL root bridges have their MMIO base address described by platform > > firmware. Refactor the existing register lookup into a generic facility > > for endpoints and bridges to share. > > > > Reviewed-by: Ben Widawsky <ben.widawsky@xxxxxxxxx> > > Signed-off-by: Dan Williams <dan.j.williams@xxxxxxxxx> > > Nice to make the docs kernel-doc, but otherwise this is simple and makes sense > > Reviewed-by: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx> > > > --- > > drivers/cxl/core.c | 57 +++++++++++++++++++++++++++++++++++++++++++++++++++- > > drivers/cxl/cxl.h | 3 +++ > > drivers/cxl/mem.c | 50 +++++----------------------------------------- > > 3 files changed, 65 insertions(+), 45 deletions(-) > > > > diff --git a/drivers/cxl/core.c b/drivers/cxl/core.c > > index 7f8d2034038a..2ab467ef9909 100644 > > --- a/drivers/cxl/core.c > > +++ b/drivers/cxl/core.c > > @@ -1,7 +1,8 @@ > > // SPDX-License-Identifier: GPL-2.0-only > > -/* Copyright(c) 2020 Intel Corporation. All rights reserved. */ > > +/* Copyright(c) 2020-2021 Intel Corporation. All rights reserved. */ > > #include <linux/device.h> > > #include <linux/module.h> > > +#include "cxl.h" > > > > /** > > * DOC: cxl core > > @@ -10,6 +11,60 @@ > > * point for cross-device interleave coordination through cxl ports. > > */ > > > > +/* > > + * cxl_setup_device_regs() - Detect CXL Device register blocks > > + * @dev: Host device of the @base mapping > > + * @base: mapping of CXL 2.0 8.2.8 CXL Device Register Interface > > Not much to add to make this kernel-doc. Just the one missing parameter > and mark it /** Given it's exported, it would be nice to tidy that up. Will do, thanks.
