Hi Lorenzo, Any inputs on this ? Regards, Bharat > -----Original Message----- > From: Bharat Kumar Gogada > Sent: Tuesday, March 23, 2021 4:48 PM > To: Bharat Kumar Gogada <bharat.kumar.gogada@xxxxxxxxxx>; linux- > pci@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx > Cc: bhelgaas@xxxxxxxxxx; Lorenzo Pieralisi <lorenzo.pieralisi@xxxxxxx> > Subject: RE: [PATCH v3 1/2] PCI: xilinx-nwl: Enable coherent PCIe DMA traffic > using CCI > > Ping. > > > -----Original Message----- > > From: Bharat Kumar Gogada > > Sent: Monday, March 15, 2021 11:43 AM > > To: Bharat Kumar Gogada <bharat.kumar.gogada@xxxxxxxxxx>; linux- > > pci@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx > > Cc: bhelgaas@xxxxxxxxxx > > Subject: RE: [PATCH v3 1/2] PCI: xilinx-nwl: Enable coherent PCIe DMA > > traffic using CCI > > > > Ping. > > > > > -----Original Message----- > > > From: Bharat Kumar Gogada <bharat.kumar.gogada@xxxxxxxxxx> > > > Sent: Monday, February 22, 2021 2:18 PM > > > To: linux-pci@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx > > > Cc: bhelgaas@xxxxxxxxxx; Bharat Kumar Gogada <bharatku@xxxxxxxxxx> > > > Subject: [PATCH v3 1/2] PCI: xilinx-nwl: Enable coherent PCIe DMA > > > traffic using CCI > > > > > > Add support for routing PCIe DMA traffic coherently when Cache > > > Coherent Interconnect (CCI) is enabled in the system. > > > The "dma-coherent" property is used to determine if CCI is enabled or > not. > > > Refer to https://developer.arm.com/documentation/ddi0470/k/preface > > > for the CCI specification. > > > > > > Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xxxxxxxxxx> > > > --- > > > drivers/pci/controller/pcie-xilinx-nwl.c | 7 +++++++ > > > 1 file changed, 7 insertions(+) > > > > > > diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c > > > b/drivers/pci/controller/pcie-xilinx-nwl.c > > > index 07e36661bbc2..8689311c5ef6 100644 > > > --- a/drivers/pci/controller/pcie-xilinx-nwl.c > > > +++ b/drivers/pci/controller/pcie-xilinx-nwl.c > > > @@ -26,6 +26,7 @@ > > > > > > /* Bridge core config registers */ > > > #define BRCFG_PCIE_RX0 0x00000000 > > > +#define BRCFG_PCIE_RX1 0x00000004 > > > #define BRCFG_INTERRUPT 0x00000010 > > > #define BRCFG_PCIE_RX_MSG_FILTER 0x00000020 > > > > > > @@ -128,6 +129,7 @@ > > > #define NWL_ECAM_VALUE_DEFAULT 12 > > > > > > #define CFG_DMA_REG_BAR GENMASK(2, 0) > > > +#define CFG_PCIE_CACHE GENMASK(7, 0) > > > > > > #define INT_PCI_MSI_NR (2 * 32) > > > > > > @@ -675,6 +677,11 @@ static int nwl_pcie_bridge_init(struct nwl_pcie > > > *pcie) > > > nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK, > > > BRCFG_PCIE_RX_MSG_FILTER); > > > > > > + /* This routes the PCIe DMA traffic to go through CCI path */ > > > + if (of_dma_is_coherent(dev->of_node)) > > > + nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, > > > BRCFG_PCIE_RX1) | > > > + CFG_PCIE_CACHE, BRCFG_PCIE_RX1); > > > + > > > err = nwl_wait_for_link(pcie); > > > if (err) > > > return err; > > > -- > > > 2.17.1
