Em Fri, 26 Mar 2021 14:21:02 +0530 Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx> escreveu: > On Fri, Mar 26, 2021 at 09:39:36AM +0100, Mauro Carvalho Chehab wrote: > > Em Wed, 3 Feb 2021 08:34:21 -0600 > > Rob Herring <robh@xxxxxxxxxx> escreveu: > > > > > On Wed, Feb 3, 2021 at 1:02 AM Mauro Carvalho Chehab > > > <mchehab+huawei@xxxxxxxxxx> wrote: > > > > > > > > From: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx> > > > > > > > > Add support for HiSilicon Kirin 970 (hi3670) SoC PCIe controller, based > > > > on Synopsys DesignWare PCIe controller IP. > > > > > > > > [mchehab+huawei@xxxxxxxxxx: fix merge conflicts] > > > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx> > > > > Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@xxxxxxxxxx> > > > > --- > > > > drivers/pci/controller/dwc/pcie-kirin.c | 723 +++++++++++++++++++++++- > > > > 1 file changed, 707 insertions(+), 16 deletions(-) > > > > > > > > diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c > > > > index 026fd1e42a55..5925d2b345a8 100644 > > > > --- a/drivers/pci/controller/dwc/pcie-kirin.c > > > > +++ b/drivers/pci/controller/dwc/pcie-kirin.c > > > > @@ -29,6 +29,7 @@ > > > > > [...] > > > > This looks like it is almost all phy related. I think it should all be > > > moved to a separate phy driver. Yes, we have some other PCI drivers > > > controlling their phys directly where the phy registers are > > > intermingled with the PCI host registers, but I think those either > > > predate the phy subsystem or are really simple. I also have a dream to > > > move all the phy control to the DWC core code. > > > > Please notice that this patch was not written by me, but, instead, > > by Mannivannan. So, I can't change it. > > Feel free to move the PHY pieces to a separate PHY driver as suggested. > My driver code was merely WIP one and I don't have any objection to > change the patch. > > I'd be happy if you add my Co-developed tag to the PCIe driver patch with > the SoB ofc. Ok. > > What I can certainly do is to > > write a separate patch at the end of this series moving the Kirin 970 > > phy to a separate driver. Would this be accepted? > > > > Ah, please don't do that. I know that you've already followed the same > process for other HiSi drivers but that looks messy IMO. The problem is related to licensing issues and US export regulations. By preserving the patches from the original authors, I played safe. > > > Btw, what should be done with the Kirin 960 PHY code that it is > > already embedded on this driver, and whose some of the DT properties > > are for its phy layer? > > > > You might need to create a PHY driver for both 960 and 970. I don't see > any harm there. But please make sure you test the patches on both boards. Testing on Kirin 960 will be harder. Well, I can get my hands on one such board, but right now I don't have any M.2 device I can spare with, in order to test. This will also break DT backward compatibility, as, for instance, the PERST# gpio seems to be part of the Kirin 960 PHY, as Kirin 970 has different PERST# logic: on Kirin 970, there's one PERST# GPIO per PCIe device. So, before starting such change, I need to know if DT maintainers are OK with that. Thanks, Mauro
