Hi Kishon,
A few small nitpicks.
> Errata #i2037 in AM65x/DRA80xM Processors Silicon Revision 1.0
> (SPRZ452D–July 2018–Revised December 2019 [1]) mentions when an
> inbound PCIe TLP spans more than two internal AXI 128-byte bursts,
> the bus may corrupt the packet payload and the corrupt data may
> cause associated applications or the processor to hang.
>
> The workaround for Errata #i2037 is to limit the maximum read
> request size and maximum payload size to 128 Bytes. Add workaround
> for Errata #i2037 here. The errata and workaround is applicable
> only to AM65x SR 1.0 and later versions of the silicon will have
> this fixed.
I think it would be either "128 B" or "128 bytes", there is no need to
capitalise bytes.
[...]
> + /*
> + * Memory transactions fail with PCI controller in AM654 PG1.0
> + * when MRRS is set to more than 128 Bytes. Force the MRRS to
> + * 128 Bytes in all downstream devices.
> + */
Same here, it would be "128 bytes" in the comment above.
[...]
> + if (pcie_get_readrq(dev) > 128) {
> + dev_info(&dev->dev, "limiting MRRS to 128\n");
> + pcie_set_readrq(dev, 128);
> + }
[...]
Might be nice to add unit here, so "128 bytes".
Krzysztof
