On Thu, Mar 25 2021 at 17:08, Marc Zyngier wrote:
> Megha Dey <megha.dey@xxxxxxxxx> wrote:
>> @@ -434,6 +434,12 @@ int __msi_domain_alloc_irqs(struct irq_domain *domain, struct device *dev,
>> if (ret)
>> return ret;
>>
>> + if (ops->msi_alloc_store) {
>> + ret = ops->msi_alloc_store(domain, dev, nvec);
>
> What is supposed to happen if we get aliasing devices (similar to what
> we have with devices behind a PCI bridge)?
>
> The ITS code goes through all kind of hoops to try and detect this
> case when sizing the translation tables (in the .prepare callback),
> and I have the feeling that sizing the message store is analogous.
No. The message store itself is sized upfront by the underlying 'master'
device. Each 'master' device has it's own irqdomain.
This is the allocation for the subdevice and this is not part of PCI and
therefore not subject to PCI aliasing.
|-----------|
| PCI dev | <- driver creates irqdomain and manages MSI
|-----------| Sizing is either fixed (hardware property)
or just managed by that irqdomain/driver
with some hardware constraints
|subdev| <- subdev gets ^^irqdomain assigned and
allocates from it.
.....
|subdev|
So this is fundamentally different from ITS because ITS has to size the
translation memory, i.e. where the MSI message is written to by the
device.
IMS just handles the storage of the message in the (sub)device. So if
that needs to be supported on ARM then the issue is not with the
subdevices, the issue is with the 'master' device, but that does not use
that alloc_store() callback as it provides it with the irqdomain it
manages.
Thanks,
tglx
