Some TI KeyStone C667X devices do not support bus/hot reset. Its PCIESS automatically disables LTSSM when secondary bus reset is received and device stops working. Prevent bus reset by adding quirk_no_bus_reset to the device. With this change device can be assigned to VMs with VFIO, but it will leak state between VMs. Reference: https://e2e.ti.com/support/processors/f/791/t/954382 Signed-off-by: Antti Järvinen <antti.jarvinen@xxxxxxxxx> --- drivers/pci/quirks.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 653660e3ba9e..d9201ad1ca39 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -3578,6 +3578,16 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset); */ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset); +/* + * Some TI keystone C667X devices do no support bus/hot reset. + * Its PCIESS automatically disables LTSSM when secondary bus reset is + * received and device stops working. Prevent bus reset by adding + * quirk_no_bus_reset to the device. With this change device can be + * assigned to VMs with VFIO, but it will leak state between VMs. + * Reference https://e2e.ti.com/support/processors/f/791/t/954382 + */ +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0xb005, quirk_no_bus_reset); + static void quirk_no_pm_reset(struct pci_dev *dev) { /* -- 2.17.1
